2018-09-28 22:06:35 +00:00
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; Copyright 2018 David Schmidt. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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;
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; Adapted from Apple /// reference materials
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2018-09-28 23:43:33 +00:00
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;
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2018-09-28 22:06:35 +00:00
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*SYNOPSIS Symbols from hardware I/O areas
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2020-08-22 20:56:57 +00:00
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KBD @ $C000 ;last key pressed (KA Data)
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KBDBFLG @ $C008 ;KB data
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2018-09-29 04:10:37 +00:00
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KBDSTRB @ $C010 ;RW keyboard strobe
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SPKR @ $C030 ;RW toggle speaker (Apple II type)
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2018-09-29 04:31:32 +00:00
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SPKRIII @ $C040 ;RW beeps speaker (Apple /// type)
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2020-08-22 20:56:57 +00:00
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CLRTEXTGR @ $C050 ;Clear TEXT/GR mode
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SETTEXTGR @ $C051 ;Set TEXT/GR mode
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CLRMIX @ $C052 ;Clear MIX mode
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SETMIX @ $C053 ;Set MIX mode
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CLRPAGE2 @ $C054 ;Clear PAGE2 mode
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SETPAGE2 @ $C055 ;Set PAGE2 mode
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CLRHIRES @ $C056 ;Clear HIRES mode
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SETHIRES @ $C057 ;Set HIRES mode
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CLRPDL0 @ $C058 ;Clear PDL0 (A/D Addr 0)
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SETPDL0 @ $C059 ;Set PDL0 (A/D Addr 0)
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CLRPDL2 @ $C05A ;Clear PDL2 (A/D Addr 2)
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SETPDL2 @ $C05B ;Set PDL2 (A/D Addr 2)
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CLRPDLEN @ $C05C ;Clear PDLEN (A/D Ramp Start)
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SETPDLEN @ $C05D ;Set PDLEN (A/D Ramp Start)
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CLRPDL1 @ $C05E ;Clear PDL1 (A/D Addr 1)
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SETPDL1 @ $C05F ;Set PDL1 (A/D Addr 1)
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READSW0 @ $C060 ;Read SW0
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READSW1 @ $C061 ;Read SW1/MGNSW
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READSW2 @ $C062 ;Read SW2
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READSW3 @ $C063 ;Read SW3/SCO
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JOYRDY @ $C066 ;Read PDLOT (A/D Ramp Stop)
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2018-09-29 04:10:37 +00:00
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CLOCK @ $C070 ;clock
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PHASOFF @ $C080 ;
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PHASON @ $C081 ;
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MOTOROFF @ $C088 ;
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MOTORON @ $C089 ;
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DRV0EN @ $C08A ;
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DRV1EN @ $C08B ;
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Q6L @ $C08C ;
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Q6H @ $C08D ;
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Q7L @ $C08E ;
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2020-08-22 20:56:57 +00:00
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CLRDSA0 @ $C0D0 ;Clear Drive Select A0
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SETDSA0 @ $C0D1 ;Set Drive Select A0
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CLRDSA1 @ $C0D2 ;Clear Drive Select A1
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SETDSA1 @ $C0D3 ;Set Drive Select A1
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CLREN1INT @ $C0D4 ;
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SETEN1INT @ $C0D5 ;
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CLRSIDE2 @ $C0D6 ;
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SETSIDE2 @ $C0D7 ;
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CLRSCR @ $C0D8 ;Clear Smooth Scroll (to turn smooth scroll off)
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SETSCR @ $C0D9 ;Set Smooth Scroll (to turn smooth scroll on)
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CLRENCWRT @ $C0DA ;Clear Char Set writing
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SETENCWRT @ $C0DB ;Set Char Set writing
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CLRENSEL @ $C0DC ;Clear enable silentype port (ENSEL)
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SETENSEL @ $C0DD ;Set enable silentype port (ENSEL)
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CLRENSIO @ $C0DE ;Clear enable silentype port (ENSIO)
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SETENSIO @ $C0DF ;Set enable silentype port (ENSIO)
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ACIADATA @ $C0F0 ;ACIA DATA REGISTER
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ACIASTAT @ $C0F1 ;ACIA STATUS REGISTER
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ACIACMD @ $C0F2 ;ACIA COMMAND REGISTER
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ACIACTL @ $C0F3 ;ACIA CONTROL REGISTER
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2018-09-28 22:06:35 +00:00
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; Other hardware registers
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2020-08-22 20:56:57 +00:00
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Z_REG @ $FFD0 ;zero page register
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D_DDRB @ $FFD2 ;data direction register B
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D_DDRA @ $FFD3 ;data direction register A
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D_TIMER1C_L @ $FFD4
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D_TIMER1C_H @ $FFD5
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D_TIMER1L_L @ $FFD6
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D_TIMER1L_H @ $FFD7
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D_TIMER2C_L @ $FFD8
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D_TIMER2C_H @ $FFD9
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D_ACR @ $FFDB
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D_PCR @ $FFDC
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D_IFR @ $FFDD
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D_IER @ $FFDE
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E_REG @ $FFDF ;environment register
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E_IORB @ $FFE0
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E_DDRB @ $FFE2
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E_DDRA @ $FFE3
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E_TIMER1C_L @ $FFE6
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E_TIMER1C_H @ $FFE7
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E_TIMER1L_L @ $FFE6
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E_TIMER1L_H @ $FFE7
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E_TIMER2C_L @ $FFE8
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E_TIMER2C_H @ $FFE9
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E_ACR @ $FFEB
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E_PCR @ $FFEC
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E_IFR @ $FFED
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E_IER @ $FFEE
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B_REG @ $FFEF ;bank switch register
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