6502bench/SourceGen/SGTestData/Expected/20252-nested-regions_cc65.S

         .setcpu "65816"
         .org    $031000
         .a8
         .i8
L31000:  lda     L31000
@L31004: lda     @L31004
         and     f:@L1101F
         jml     @L21010

         .org    $021010
@L21010: lda     @L21010
         jml     @L11018

         .org    $011018
@L11018: lda     @L11018
         jmp     @L11026 & $ffff

@L1101F: .byte   $80
         .org    $0000
         .byte   $ea
         .byte   $60
         .dword  @L31004

         .org    $011026
@L11026: nop
         rts
ORG rework, part 7 Implemented "is relative" flag. This only affects source code generation, replacing ".arstart <addr>" with ".arstart *+<value>". Only output by 64tass and ACME generators. Added a bold-text summary to radio buttons in address region edit dialog. This makes it much easier to see what you're doing. Added a warning to the label edit dialog when a label is being placed in a non-addressable region. Modified double-click behavior for .arstart/.arend to jump to the other end when the opcode is clicked on. This matches the behavior of instructions with address operands. Reordered Actions menu, putting "edit operand" at the top. Fixed AddressMap entry collision testing. Fixed PRG issue with multiple address regions at offset +000002. Added regression tests. Most of the complicated stuff with regions is tested by unit tests inside AddressMap, but we still need to exercise nested region code generation. 2021-10-02 20:47:05 +00:00			`.setcpu "65816"`
			`.org $031000`
			`.a8`
			`.i8`
			`L31000: lda L31000`
			`@L31004: lda @L31004`
			`and f:@L1101F`
			`jml @L21010`

			`.org $021010`
			`@L21010: lda @L21010`
			`jml @L11018`

			`.org $011018`
			`@L11018: lda @L11018`
			`jmp @L11026 & $ffff`

			`@L1101F: .byte $80`
			`.org $0000`
			`.byte $ea`
			`.byte $60`
			`.dword @L31004`

			`.org $011026`
			`@L11026: nop`
			`rts`