6502bench/SourceGen/SGTestData/Expected/20252-nested-regions_64tass.S

        .cpu    "65816"
        .logical $011000
        .logical *+$010000
        .logical *+$010000
        .as
        .xs
L31000  lda     L31000
_L31004 lda     _L31004
        and     _L1101F
        jml     _L21010

        .here
_L21010 lda     _L21010
        jml     _L11018

        .here
_L11018 lda     _L11018
        jmp     _L11026

_L1101F .byte   $80
        .logical *-$011020
        .byte   $ea
        .byte   $60
        .dword  _L31004
        .here

_L11026 nop
        rts

        .here
ORG rework, part 7 Implemented "is relative" flag. This only affects source code generation, replacing ".arstart <addr>" with ".arstart *+<value>". Only output by 64tass and ACME generators. Added a bold-text summary to radio buttons in address region edit dialog. This makes it much easier to see what you're doing. Added a warning to the label edit dialog when a label is being placed in a non-addressable region. Modified double-click behavior for .arstart/.arend to jump to the other end when the opcode is clicked on. This matches the behavior of instructions with address operands. Reordered Actions menu, putting "edit operand" at the top. Fixed AddressMap entry collision testing. Fixed PRG issue with multiple address regions at offset +000002. Added regression tests. Most of the complicated stuff with regions is tested by unit tests inside AddressMap, but we still need to exercise nested region code generation. 2021-10-02 20:47:05 +00:00			`.cpu "65816"`
			`.logical $011000`
			`.logical *+$010000`
			`.logical *+$010000`
			`.as`
			`.xs`
			`L31000 lda L31000`
			`_L31004 lda _L31004`
			`and _L1101F`
			`jml _L21010`

			`.here`
			`_L21010 lda _L21010`
			`jml _L11018`

			`.here`
			`_L11018 lda _L11018`
			`jmp _L11026`

			`_L1101F .byte $80`
			`.logical *-$011020`
			`.byte $ea`
			`.byte $60`
			`.dword _L31004`
			`.here`

			`_L11026 nop`
			`rts`

			`.here`