diff --git a/SourceGen/SGTestData/10020-embedded-instructions b/SourceGen/SGTestData/10020-embedded-instructions
new file mode 100644
index 0000000..d42a54c
Binary files /dev/null and b/SourceGen/SGTestData/10020-embedded-instructions differ
diff --git a/SourceGen/SGTestData/10022-embedded-instructions b/SourceGen/SGTestData/10022-embedded-instructions
index cffff3c..b8878e2 100644
Binary files a/SourceGen/SGTestData/10022-embedded-instructions and b/SourceGen/SGTestData/10022-embedded-instructions differ
diff --git a/SourceGen/SGTestData/10030-flags-and-branches b/SourceGen/SGTestData/10030-flags-and-branches
new file mode 100644
index 0000000..621b7aa
Binary files /dev/null and b/SourceGen/SGTestData/10030-flags-and-branches differ
diff --git a/SourceGen/SGTestData/10032-flags-and-branches b/SourceGen/SGTestData/10032-flags-and-branches
index 6528821..717caa7 100644
Binary files a/SourceGen/SGTestData/10032-flags-and-branches and b/SourceGen/SGTestData/10032-flags-and-branches differ
diff --git a/SourceGen/SGTestData/Expected/10020-embedded-instructions_64tass.S b/SourceGen/SGTestData/Expected/10020-embedded-instructions_64tass.S
new file mode 100644
index 0000000..ebe3882
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10020-embedded-instructions_64tass.S
@@ -0,0 +1,61 @@
+        .cpu    "6502i"
+*       =       $1000
+        jsr     L100F
+        jsr     L1017
+        jsr     L101C
+        jsr     L1046
+        jmp     L1051
+
+L100F   lda     #$00
+        .byte   $2c
+_L1012  lda     #$01
+        beq     _L1012
+        rts
+
+L1017   .byte   $20
+_L1018  rts
+
+        .byte   $ea
+        bvs     _L1018
+L101C   .byte   $2c
+_L101D  .byte   $2c
+_L101E  .byte   $2c
+_L101F  .byte   $2c
+_L1020  .byte   $2c
+_L1021  .byte   $2c
+_L1022  .byte   $2c
+_L1023  .byte   $2c
+_L1024  .byte   $2c
+_L1025  nop
+        nop
+        asl     a
+        bcc     L101C
+        asl     a
+        bcc     _L101D
+        asl     a
+        bcc     _L101E
+        asl     a
+        bcc     _L101F
+        asl     a
+        bcc     _L1020
+        asl     a
+        bcc     _L1021
+        asl     a
+        bcc     _L1022
+        asl     a
+        bcc     _L1023
+        asl     a
+        bcc     _L1024
+        asl     a
+        bcc     _L1025
+        rts
+
+L1046   .byte   $2c
+_L1047  nop
+        .byte   $ad
+_L1049  lda     $00
+        asl     a
+        bcc     _L1047
+        asl     a
+        bcc     _L1049
+L1051   .byte   $ad
diff --git a/SourceGen/SGTestData/Expected/10020-embedded-instructions_acme.S b/SourceGen/SGTestData/Expected/10020-embedded-instructions_acme.S
new file mode 100644
index 0000000..36d4ece
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10020-embedded-instructions_acme.S
@@ -0,0 +1,61 @@
+        !cpu    6510
+*       =       $1000
+        jsr     L100F
+        jsr     L1017
+        jsr     L101C
+        jsr     L1046
+        jmp     L1051
+
+L100F   lda     #$00
+        !byte   $2c
+@L1012  lda     #$01
+        beq     @L1012
+        rts
+
+L1017   !byte   $20
+@L1018  rts
+
+        !byte   $ea
+        bvs     @L1018
+L101C   !byte   $2c
+@L101D  !byte   $2c
+@L101E  !byte   $2c
+@L101F  !byte   $2c
+@L1020  !byte   $2c
+@L1021  !byte   $2c
+@L1022  !byte   $2c
+@L1023  !byte   $2c
+@L1024  !byte   $2c
+@L1025  nop
+        nop
+        asl
+        bcc     L101C
+        asl
+        bcc     @L101D
+        asl
+        bcc     @L101E
+        asl
+        bcc     @L101F
+        asl
+        bcc     @L1020
+        asl
+        bcc     @L1021
+        asl
+        bcc     @L1022
+        asl
+        bcc     @L1023
+        asl
+        bcc     @L1024
+        asl
+        bcc     @L1025
+        rts
+
+L1046   !byte   $2c
+@L1047  nop
+        !byte   $ad
+@L1049  lda     $00
+        asl
+        bcc     @L1047
+        asl
+        bcc     @L1049
+L1051   !byte   $ad
diff --git a/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.S b/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.S
new file mode 100644
index 0000000..0594f42
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.S
@@ -0,0 +1,62 @@
+         .setcpu "6502X"
+;         .segment "SEG000"
+         .org    $1000
+         jsr     L100F
+         jsr     L1017
+         jsr     L101C
+         jsr     L1046
+         jmp     L1051
+
+L100F:   lda     #$00
+         .byte   $2c
+@L1012:  lda     #$01
+         beq     @L1012
+         rts
+
+L1017:   .byte   $20
+@L1018:  rts
+
+         .byte   $ea
+         bvs     @L1018
+L101C:   .byte   $2c
+@L101D:  .byte   $2c
+@L101E:  .byte   $2c
+@L101F:  .byte   $2c
+@L1020:  .byte   $2c
+@L1021:  .byte   $2c
+@L1022:  .byte   $2c
+@L1023:  .byte   $2c
+@L1024:  .byte   $2c
+@L1025:  nop
+         nop
+         asl     A
+         bcc     L101C
+         asl     A
+         bcc     @L101D
+         asl     A
+         bcc     @L101E
+         asl     A
+         bcc     @L101F
+         asl     A
+         bcc     @L1020
+         asl     A
+         bcc     @L1021
+         asl     A
+         bcc     @L1022
+         asl     A
+         bcc     @L1023
+         asl     A
+         bcc     @L1024
+         asl     A
+         bcc     @L1025
+         rts
+
+L1046:   .byte   $2c
+@L1047:  nop
+         .byte   $ad
+@L1049:  lda     $00
+         asl     A
+         bcc     @L1047
+         asl     A
+         bcc     @L1049
+L1051:   .byte   $ad
diff --git a/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.cfg b/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.cfg
new file mode 100644
index 0000000..7325f97
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.cfg
@@ -0,0 +1,11 @@
+# 6502bench SourceGen generated linker script for 10020-embedded-instructions
+MEMORY {
+    MAIN: file=%O, start=%S, size=65536;
+#    MEM000: file=%O, start=$1000, size=82;
+}
+SEGMENTS {
+    CODE: load=MAIN, type=rw;
+#    SEG000: load=MEM000, type=rw;
+}
+FEATURES {}
+SYMBOLS {}
diff --git a/SourceGen/SGTestData/Expected/10020-embedded-instructions_merlin32.S b/SourceGen/SGTestData/Expected/10020-embedded-instructions_merlin32.S
new file mode 100644
index 0000000..1d3360d
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10020-embedded-instructions_merlin32.S
@@ -0,0 +1,60 @@
+         org   $1000
+         jsr   L100F
+         jsr   L1017
+         jsr   L101C
+         jsr   L1046
+         jmp   L1051
+
+L100F    lda   #$00
+         dfb   $2c
+:L1012   lda   #$01
+         beq   :L1012
+         rts
+
+L1017    dfb   $20
+:L1018   rts
+
+         dfb   $ea
+         bvs   :L1018
+L101C    dfb   $2c
+:L101D   dfb   $2c
+:L101E   dfb   $2c
+:L101F   dfb   $2c
+:L1020   dfb   $2c
+:L1021   dfb   $2c
+:L1022   dfb   $2c
+:L1023   dfb   $2c
+:L1024   dfb   $2c
+:L1025   nop
+         nop
+         asl   A
+         bcc   L101C
+         asl   A
+         bcc   :L101D
+         asl   A
+         bcc   :L101E
+         asl   A
+         bcc   :L101F
+         asl   A
+         bcc   :L1020
+         asl   A
+         bcc   :L1021
+         asl   A
+         bcc   :L1022
+         asl   A
+         bcc   :L1023
+         asl   A
+         bcc   :L1024
+         asl   A
+         bcc   :L1025
+         rts
+
+L1046    dfb   $2c
+:L1047   nop
+         dfb   $ad
+:L1049   lda   $00
+         asl   A
+         bcc   :L1047
+         asl   A
+         bcc   :L1049
+L1051    dfb   $ad
diff --git a/SourceGen/SGTestData/Expected/10022-embedded-instructions_64tass.S b/SourceGen/SGTestData/Expected/10022-embedded-instructions_64tass.S
index 39c12f4..7f72582 100644
--- a/SourceGen/SGTestData/Expected/10022-embedded-instructions_64tass.S
+++ b/SourceGen/SGTestData/Expected/10022-embedded-instructions_64tass.S
@@ -2,76 +2,24 @@
 *       =       $1000
         .as
         .xs
-        clc
-        xce
-        sep     #$30
-        jsr     L1014
-        jsr     L101C
-        jsr     L102A
-        jsr     L102F
-        jsr     L1059
-        rts
+        jsr     L1006
+        jmp     L1020
 
-L1014   lda     #$00
-        .byte   $2c
-_L1017  lda     #$01
-        beq     _L1017
-        rts
-
-L101C   sep     #$30
+L1006   sep     #$30
         lda     $00
-        beq     _L1025
+        beq     _L100F
         lda     #$00
         brk
 
-_L1025  sta     $012345
-        rts
-
-L102A   .byte   $20
-_L102B  rts
-
-        .byte   $ea
-        bra     _L102B
-
-L102F   .byte   $2c
-_L1030  .byte   $2c
-_L1031  .byte   $2c
-_L1032  .byte   $2c
-_L1033  .byte   $2c
-_L1034  .byte   $2c
-_L1035  .byte   $2c
-_L1036  .byte   $2c
-_L1037  .byte   $2c
-_L1038  nop
+_L100F  sta     $012345
+        lda     $00
+        beq     _L101A
+        lda     #$00
+        .byte   $85
+_L101A  .byte   $8f
+        eor     $23
+        .byte   $01
         nop
-        asl     a
-        bcc     L102F
-        asl     a
-        bcc     _L1030
-        asl     a
-        bcc     _L1031
-        asl     a
-        bcc     _L1032
-        asl     a
-        bcc     _L1033
-        asl     a
-        bcc     _L1034
-        asl     a
-        bcc     _L1035
-        asl     a
-        bcc     _L1036
-        asl     a
-        bcc     _L1037
-        asl     a
-        bcc     _L1038
         rts
 
-L1059   .byte   $2c
-_L105A  nop
-        .byte   $ad
-_L105C  lda     $00
-        asl     a
-        bcc     _L105A
-        asl     a
-        bcc     _L105C
-        .byte   $af
+L1020   .byte   $af
diff --git a/SourceGen/SGTestData/Expected/10022-embedded-instructions_acme.S b/SourceGen/SGTestData/Expected/10022-embedded-instructions_acme.S
index 8b5343e..62f1758 100644
--- a/SourceGen/SGTestData/Expected/10022-embedded-instructions_acme.S
+++ b/SourceGen/SGTestData/Expected/10022-embedded-instructions_acme.S
@@ -2,76 +2,24 @@
 *       =       $1000
         !as
         !rs
-        clc
-        xce
-        sep     #$30
-        jsr     L1014
-        jsr     L101C
-        jsr     L102A
-        jsr     L102F
-        jsr     L1059
-        rts
+        jsr     L1006
+        jmp     L1020
 
-L1014   lda     #$00
-        !byte   $2c
-@L1017  lda     #$01
-        beq     @L1017
-        rts
-
-L101C   sep     #$30
+L1006   sep     #$30
         lda     $00
-        beq     @L1025
+        beq     @L100F
         lda     #$00
         brk
 
-@L1025  sta+3   $012345
-        rts
-
-L102A   !byte   $20
-@L102B  rts
-
-        !byte   $ea
-        bra     @L102B
-
-L102F   !byte   $2c
-@L1030  !byte   $2c
-@L1031  !byte   $2c
-@L1032  !byte   $2c
-@L1033  !byte   $2c
-@L1034  !byte   $2c
-@L1035  !byte   $2c
-@L1036  !byte   $2c
-@L1037  !byte   $2c
-@L1038  nop
+@L100F  sta+3   $012345
+        lda     $00
+        beq     @L101A
+        lda     #$00
+        !byte   $85
+@L101A  !byte   $8f
+        eor     $23
+        !byte   $01
         nop
-        asl
-        bcc     L102F
-        asl
-        bcc     @L1030
-        asl
-        bcc     @L1031
-        asl
-        bcc     @L1032
-        asl
-        bcc     @L1033
-        asl
-        bcc     @L1034
-        asl
-        bcc     @L1035
-        asl
-        bcc     @L1036
-        asl
-        bcc     @L1037
-        asl
-        bcc     @L1038
         rts
 
-L1059   !byte   $2c
-@L105A  nop
-        !byte   $ad
-@L105C  lda     $00
-        asl
-        bcc     @L105A
-        asl
-        bcc     @L105C
-        !byte   $af
+L1020   !byte   $af
diff --git a/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.S b/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.S
index 3c5705c..50dbefe 100644
--- a/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.S
+++ b/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.S
@@ -3,76 +3,24 @@
          .org    $1000
          .a8
          .i8
-         clc
-         xce
-         sep     #$30
-         jsr     L1014
-         jsr     L101C
-         jsr     L102A
-         jsr     L102F
-         jsr     L1059
-         rts
+         jsr     L1006
+         jmp     L1020
 
-L1014:   lda     #$00
-         .byte   $2c
-@L1017:  lda     #$01
-         beq     @L1017
-         rts
-
-L101C:   sep     #$30
+L1006:   sep     #$30
          lda     $00
-         beq     @L1025
+         beq     @L100F
          lda     #$00
          brk
 
-@L1025:  sta     $012345
-         rts
-
-L102A:   .byte   $20
-@L102B:  rts
-
-         .byte   $ea
-         bra     @L102B
-
-L102F:   .byte   $2c
-@L1030:  .byte   $2c
-@L1031:  .byte   $2c
-@L1032:  .byte   $2c
-@L1033:  .byte   $2c
-@L1034:  .byte   $2c
-@L1035:  .byte   $2c
-@L1036:  .byte   $2c
-@L1037:  .byte   $2c
-@L1038:  nop
+@L100F:  sta     $012345
+         lda     $00
+         beq     @L101A
+         lda     #$00
+         .byte   $85
+@L101A:  .byte   $8f
+         eor     $23
+         .byte   $01
          nop
-         asl     A
-         bcc     L102F
-         asl     A
-         bcc     @L1030
-         asl     A
-         bcc     @L1031
-         asl     A
-         bcc     @L1032
-         asl     A
-         bcc     @L1033
-         asl     A
-         bcc     @L1034
-         asl     A
-         bcc     @L1035
-         asl     A
-         bcc     @L1036
-         asl     A
-         bcc     @L1037
-         asl     A
-         bcc     @L1038
          rts
 
-L1059:   .byte   $2c
-@L105A:  nop
-         .byte   $ad
-@L105C:  lda     $00
-         asl     A
-         bcc     @L105A
-         asl     A
-         bcc     @L105C
-         .byte   $af
+L1020:   .byte   $af
diff --git a/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.cfg b/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.cfg
index 0c180db..2ae844f 100644
--- a/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.cfg
+++ b/SourceGen/SGTestData/Expected/10022-embedded-instructions_cc65.cfg
@@ -1,7 +1,7 @@
 # 6502bench SourceGen generated linker script for 10022-embedded-instructions
 MEMORY {
     MAIN: file=%O, start=%S, size=65536;
-#    MEM000: file=%O, start=$1000, size=101;
+#    MEM000: file=%O, start=$1000, size=33;
 }
 SEGMENTS {
     CODE: load=MAIN, type=rw;
diff --git a/SourceGen/SGTestData/Expected/10022-embedded-instructions_merlin32.S b/SourceGen/SGTestData/Expected/10022-embedded-instructions_merlin32.S
index 7bd4229..5277962 100644
--- a/SourceGen/SGTestData/Expected/10022-embedded-instructions_merlin32.S
+++ b/SourceGen/SGTestData/Expected/10022-embedded-instructions_merlin32.S
@@ -1,74 +1,22 @@
          org   $1000
-         clc
-         xce
-         sep   #$30
-         jsr   L1014
-         jsr   L101C
-         jsr   L102A
-         jsr   L102F
-         jsr   L1059
-         rts
+         jsr   L1006
+         jmp   L1020
 
-L1014    lda   #$00
-         dfb   $2c
-:L1017   lda   #$01
-         beq   :L1017
-         rts
-
-L101C    sep   #$30
+L1006    sep   #$30
          lda   $00
-         beq   :L1025
+         beq   :L100F
          lda   #$00
          brk
 
-:L1025   stal  $012345
-         rts
-
-L102A    dfb   $20
-:L102B   rts
-
-         dfb   $ea
-         bra   :L102B
-
-L102F    dfb   $2c
-:L1030   dfb   $2c
-:L1031   dfb   $2c
-:L1032   dfb   $2c
-:L1033   dfb   $2c
-:L1034   dfb   $2c
-:L1035   dfb   $2c
-:L1036   dfb   $2c
-:L1037   dfb   $2c
-:L1038   nop
+:L100F   stal  $012345
+         lda   $00
+         beq   :L101A
+         lda   #$00
+         dfb   $85
+:L101A   dfb   $8f
+         eor   $23
+         dfb   $01
          nop
-         asl   A
-         bcc   L102F
-         asl   A
-         bcc   :L1030
-         asl   A
-         bcc   :L1031
-         asl   A
-         bcc   :L1032
-         asl   A
-         bcc   :L1033
-         asl   A
-         bcc   :L1034
-         asl   A
-         bcc   :L1035
-         asl   A
-         bcc   :L1036
-         asl   A
-         bcc   :L1037
-         asl   A
-         bcc   :L1038
          rts
 
-L1059    dfb   $2c
-:L105A   nop
-         dfb   $ad
-:L105C   lda   $00
-         asl   A
-         bcc   :L105A
-         asl   A
-         bcc   :L105C
-         dfb   $af
+L1020    dfb   $af
diff --git a/SourceGen/SGTestData/Expected/10030-flags-and-branches_64tass.S b/SourceGen/SGTestData/Expected/10030-flags-and-branches_64tass.S
new file mode 100644
index 0000000..5068cc7
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10030-flags-and-branches_64tass.S
@@ -0,0 +1,175 @@
+        .cpu    "6502i"
+*       =       $1000
+        clv
+        cld
+        cli
+        clc
+        lda     #$80
+        lda     #$01
+        sed
+        sei
+        sec
+        lda     #$ff
+        adc     #$00
+        lda     #$00
+        pha
+        plp
+        clv
+        bvc     L101A
+
+        .byte   $70
+        .byte   $02
+        .byte   $00
+        .byte   $00
+
+L101A   clc
+        bcc     _L101F
+
+        .byte   $00
+        .byte   $00
+
+_L101F  sec
+        bcs     _L1024
+
+        .byte   $00
+        .byte   $00
+
+_L1024  lda     #$01
+        bne     _L102A
+
+        .byte   $00
+        .byte   $db
+
+_L102A  lda     #$00
+        beq     _L1030
+
+        .byte   $00
+        .byte   $db
+
+_L1030  bpl     _L1034
+
+        .byte   $00
+        .byte   $db
+
+_L1034  lda     #$80
+        bmi     _L103A
+
+        .byte   $00
+        .byte   $db
+
+_L103A  lda     #$ff
+        and     #$00
+        beq     _L1042
+
+        .byte   $00
+        .byte   $db
+
+_L1042  lda     #$00
+        ldx     #$80
+        and     #$ff
+        beq     _L104C
+        bne     _L104C
+
+_L104C  lda     #$ff
+        ldx     #$00
+        and     #$7f
+        beq     _L1056
+        bne     _L1056
+
+_L1056  bpl     _L105A
+
+        .byte   $00
+        .byte   $db
+
+_L105A  lda     #$ff
+        and     #$80
+        bpl     _L1064
+        bmi     _L1064
+
+        .byte   $00
+        .byte   $db
+
+_L1064  lda     #$00
+        ldx     #$80
+        bne     _L106C
+
+        .byte   $00
+        .byte   $db
+
+_L106C  ora     #$00
+        beq     _L1072
+        bne     _L1072
+
+_L1072  ora     #$01
+        bne     _L1078
+
+        .byte   $00
+        .byte   $db
+
+_L1078  lda     #$00
+        ldx     #$80
+        bmi     _L1080
+
+        .byte   $00
+        .byte   $db
+
+_L1080  ora     #$7f
+        bpl     _L1088
+        bmi     _L1088
+
+        .byte   $00
+        .byte   $db
+
+_L1088  ora     #$80
+        bmi     _L108E
+
+        .byte   $00
+        .byte   $db
+
+_L108E  lda     _L108E
+        sec
+        ror     a
+        bmi     _L1097
+
+        .byte   $00
+        .byte   $dc
+
+_L1097  clc
+        ror     a
+        bpl     _L109D
+
+        .byte   $00
+        .byte   $dc
+
+_L109D  lda     #$00
+        sec
+        rol     a
+        bne     _L10A5
+
+        .byte   $00
+        .byte   $dc
+
+_L10A5  lda     #$ff
+        lsr     a
+        bpl     _L10AC
+
+        .byte   $00
+        .byte   $dd
+
+_L10AC  clc
+        php
+        sec
+        plp
+        bcc     _L10B3
+        nop
+_L10B3  sec
+        bcs     _L10B7
+
+_L10B6  clc
+_L10B7  lda     $33
+        beq     _L10B6
+        bcs     _L10BF
+        lda     $44
+_L10BF  nop
+        rts
+
diff --git a/SourceGen/SGTestData/Expected/10030-flags-and-branches_acme.S b/SourceGen/SGTestData/Expected/10030-flags-and-branches_acme.S
new file mode 100644
index 0000000..0675462
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10030-flags-and-branches_acme.S
@@ -0,0 +1,175 @@
+        !cpu    6510
+*       =       $1000
+        clv
+        cld
+        cli
+        clc
+        lda     #$80
+        lda     #$01
+        sed
+        sei
+        sec
+        lda     #$ff
+        adc     #$00
+        lda     #$00
+        pha
+        plp
+        clv
+        bvc     L101A
+
+        !byte   $70
+        !byte   $02
+        !byte   $00
+        !byte   $00
+
+L101A   clc
+        bcc     @L101F
+
+        !byte   $00
+        !byte   $00
+
+@L101F  sec
+        bcs     @L1024
+
+        !byte   $00
+        !byte   $00
+
+@L1024  lda     #$01
+        bne     @L102A
+
+        !byte   $00
+        !byte   $db
+
+@L102A  lda     #$00
+        beq     @L1030
+
+        !byte   $00
+        !byte   $db
+
+@L1030  bpl     @L1034
+
+        !byte   $00
+        !byte   $db
+
+@L1034  lda     #$80
+        bmi     @L103A
+
+        !byte   $00
+        !byte   $db
+
+@L103A  lda     #$ff
+        and     #$00
+        beq     @L1042
+
+        !byte   $00
+        !byte   $db
+
+@L1042  lda     #$00
+        ldx     #$80
+        and     #$ff
+        beq     @L104C
+        bne     @L104C
+
+@L104C  lda     #$ff
+        ldx     #$00
+        and     #$7f
+        beq     @L1056
+        bne     @L1056
+
+@L1056  bpl     @L105A
+
+        !byte   $00
+        !byte   $db
+
+@L105A  lda     #$ff
+        and     #$80
+        bpl     @L1064
+        bmi     @L1064
+
+        !byte   $00
+        !byte   $db
+
+@L1064  lda     #$00
+        ldx     #$80
+        bne     @L106C
+
+        !byte   $00
+        !byte   $db
+
+@L106C  ora     #$00
+        beq     @L1072
+        bne     @L1072
+
+@L1072  ora     #$01
+        bne     @L1078
+
+        !byte   $00
+        !byte   $db
+
+@L1078  lda     #$00
+        ldx     #$80
+        bmi     @L1080
+
+        !byte   $00
+        !byte   $db
+
+@L1080  ora     #$7f
+        bpl     @L1088
+        bmi     @L1088
+
+        !byte   $00
+        !byte   $db
+
+@L1088  ora     #$80
+        bmi     @L108E
+
+        !byte   $00
+        !byte   $db
+
+@L108E  lda     @L108E
+        sec
+        ror
+        bmi     @L1097
+
+        !byte   $00
+        !byte   $dc
+
+@L1097  clc
+        ror
+        bpl     @L109D
+
+        !byte   $00
+        !byte   $dc
+
+@L109D  lda     #$00
+        sec
+        rol
+        bne     @L10A5
+
+        !byte   $00
+        !byte   $dc
+
+@L10A5  lda     #$ff
+        lsr
+        bpl     @L10AC
+
+        !byte   $00
+        !byte   $dd
+
+@L10AC  clc
+        php
+        sec
+        plp
+        bcc     @L10B3
+        nop
+@L10B3  sec
+        bcs     @L10B7
+
+@L10B6  clc
+@L10B7  lda     $33
+        beq     @L10B6
+        bcs     @L10BF
+        lda     $44
+@L10BF  nop
+        rts
+
diff --git a/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.S b/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.S
new file mode 100644
index 0000000..e164f6d
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.S
@@ -0,0 +1,176 @@
+         .setcpu "6502X"
+;         .segment "SEG000"
+         .org    $1000
+         clv
+         cld
+         cli
+         clc
+         lda     #$80
+         lda     #$01
+         sed
+         sei
+         sec
+         lda     #$ff
+         adc     #$00
+         lda     #$00
+         pha
+         plp
+         clv
+         bvc     L101A
+
+         .byte   $70
+         .byte   $02
+         .byte   $00
+         .byte   $00
+
+L101A:   clc
+         bcc     @L101F
+
+         .byte   $00
+         .byte   $00
+
+@L101F:  sec
+         bcs     @L1024
+
+         .byte   $00
+         .byte   $00
+
+@L1024:  lda     #$01
+         bne     @L102A
+
+         .byte   $00
+         .byte   $db
+
+@L102A:  lda     #$00
+         beq     @L1030
+
+         .byte   $00
+         .byte   $db
+
+@L1030:  bpl     @L1034
+
+         .byte   $00
+         .byte   $db
+
+@L1034:  lda     #$80
+         bmi     @L103A
+
+         .byte   $00
+         .byte   $db
+
+@L103A:  lda     #$ff
+         and     #$00
+         beq     @L1042
+
+         .byte   $00
+         .byte   $db
+
+@L1042:  lda     #$00
+         ldx     #$80
+         and     #$ff
+         beq     @L104C
+         bne     @L104C
+
+@L104C:  lda     #$ff
+         ldx     #$00
+         and     #$7f
+         beq     @L1056
+         bne     @L1056
+
+@L1056:  bpl     @L105A
+
+         .byte   $00
+         .byte   $db
+
+@L105A:  lda     #$ff
+         and     #$80
+         bpl     @L1064
+         bmi     @L1064
+
+         .byte   $00
+         .byte   $db
+
+@L1064:  lda     #$00
+         ldx     #$80
+         bne     @L106C
+
+         .byte   $00
+         .byte   $db
+
+@L106C:  ora     #$00
+         beq     @L1072
+         bne     @L1072
+
+@L1072:  ora     #$01
+         bne     @L1078
+
+         .byte   $00
+         .byte   $db
+
+@L1078:  lda     #$00
+         ldx     #$80
+         bmi     @L1080
+
+         .byte   $00
+         .byte   $db
+
+@L1080:  ora     #$7f
+         bpl     @L1088
+         bmi     @L1088
+
+         .byte   $00
+         .byte   $db
+
+@L1088:  ora     #$80
+         bmi     @L108E
+
+         .byte   $00
+         .byte   $db
+
+@L108E:  lda     @L108E
+         sec
+         ror     A
+         bmi     @L1097
+
+         .byte   $00
+         .byte   $dc
+
+@L1097:  clc
+         ror     A
+         bpl     @L109D
+
+         .byte   $00
+         .byte   $dc
+
+@L109D:  lda     #$00
+         sec
+         rol     A
+         bne     @L10A5
+
+         .byte   $00
+         .byte   $dc
+
+@L10A5:  lda     #$ff
+         lsr     A
+         bpl     @L10AC
+
+         .byte   $00
+         .byte   $dd
+
+@L10AC:  clc
+         php
+         sec
+         plp
+         bcc     @L10B3
+         nop
+@L10B3:  sec
+         bcs     @L10B7
+
+@L10B6:  clc
+@L10B7:  lda     $33
+         beq     @L10B6
+         bcs     @L10BF
+         lda     $44
+@L10BF:  nop
+         rts
+
diff --git a/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.cfg b/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.cfg
new file mode 100644
index 0000000..d2fa51d
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10030-flags-and-branches_cc65.cfg
@@ -0,0 +1,11 @@
+# 6502bench SourceGen generated linker script for 10030-flags-and-branches
+MEMORY {
+    MAIN: file=%O, start=%S, size=65536;
+#    MEM000: file=%O, start=$1000, size=193;
+}
+SEGMENTS {
+    CODE: load=MAIN, type=rw;
+#    SEG000: load=MEM000, type=rw;
+}
+FEATURES {}
+SYMBOLS {}
diff --git a/SourceGen/SGTestData/Expected/10030-flags-and-branches_merlin32.S b/SourceGen/SGTestData/Expected/10030-flags-and-branches_merlin32.S
new file mode 100644
index 0000000..9cfe7ef
--- /dev/null
+++ b/SourceGen/SGTestData/Expected/10030-flags-and-branches_merlin32.S
@@ -0,0 +1,174 @@
+         org   $1000
+         clv
+         cld
+         cli
+         clc
+         lda   #$80
+         lda   #$01
+         sed
+         sei
+         sec
+         lda   #$ff
+         adc   #$00
+         lda   #$00
+         pha
+         plp
+         clv
+         bvc   L101A
+
+         dfb   $70
+         dfb   $02
+         dfb   $00
+         dfb   $00
+
+L101A    clc
+         bcc   :L101F
+
+         dfb   $00
+         dfb   $00
+
+:L101F   sec
+         bcs   :L1024
+
+         dfb   $00
+         dfb   $00
+
+:L1024   lda   #$01
+         bne   :L102A
+
+         dfb   $00
+         dfb   $db
+
+:L102A   lda   #$00
+         beq   :L1030
+
+         dfb   $00
+         dfb   $db
+
+:L1030   bpl   :L1034
+
+         dfb   $00
+         dfb   $db
+
+:L1034   lda   #$80
+         bmi   :L103A
+
+         dfb   $00
+         dfb   $db
+
+:L103A   lda   #$ff
+         and   #$00
+         beq   :L1042
+
+         dfb   $00
+         dfb   $db
+
+:L1042   lda   #$00
+         ldx   #$80
+         and   #$ff
+         beq   :L104C
+         bne   :L104C
+
+:L104C   lda   #$ff
+         ldx   #$00
+         and   #$7f
+         beq   :L1056
+         bne   :L1056
+
+:L1056   bpl   :L105A
+
+         dfb   $00
+         dfb   $db
+
+:L105A   lda   #$ff
+         and   #$80
+         bpl   :L1064
+         bmi   :L1064
+
+         dfb   $00
+         dfb   $db
+
+:L1064   lda   #$00
+         ldx   #$80
+         bne   :L106C
+
+         dfb   $00
+         dfb   $db
+
+:L106C   ora   #$00
+         beq   :L1072
+         bne   :L1072
+
+:L1072   ora   #$01
+         bne   :L1078
+
+         dfb   $00
+         dfb   $db
+
+:L1078   lda   #$00
+         ldx   #$80
+         bmi   :L1080
+
+         dfb   $00
+         dfb   $db
+
+:L1080   ora   #$7f
+         bpl   :L1088
+         bmi   :L1088
+
+         dfb   $00
+         dfb   $db
+
+:L1088   ora   #$80
+         bmi   :L108E
+
+         dfb   $00
+         dfb   $db
+
+:L108E   lda   :L108E
+         sec
+         ror   A
+         bmi   :L1097
+
+         dfb   $00
+         dfb   $dc
+
+:L1097   clc
+         ror   A
+         bpl   :L109D
+
+         dfb   $00
+         dfb   $dc
+
+:L109D   lda   #$00
+         sec
+         rol   A
+         bne   :L10A5
+
+         dfb   $00
+         dfb   $dc
+
+:L10A5   lda   #$ff
+         lsr   A
+         bpl   :L10AC
+
+         dfb   $00
+         dfb   $dd
+
+:L10AC   clc
+         php
+         sec
+         plp
+         bcc   :L10B3
+         nop
+:L10B3   sec
+         bcs   :L10B7
+
+:L10B6   clc
+:L10B7   lda   $33
+         beq   :L10B6
+         bcs   :L10BF
+         lda   $44
+:L10BF   nop
+         rts
+
diff --git a/SourceGen/SGTestData/Expected/10032-flags-and-branches_64tass.S b/SourceGen/SGTestData/Expected/10032-flags-and-branches_64tass.S
index c2a4610..a7e9727 100644
--- a/SourceGen/SGTestData/Expected/10032-flags-and-branches_64tass.S
+++ b/SourceGen/SGTestData/Expected/10032-flags-and-branches_64tass.S
@@ -5,17 +5,6 @@
         clc
         xce
         sep     #$ff
-        clv
-        cld
-        cli
-        clc
-        lda     #$80
-        lda     #$01
-        sed
-        sei
-        sec
-        lda     #$ff
-        adc     #$00
         sep     #$ff
         rep     #$80
         rep     #$40
@@ -65,221 +54,93 @@
         pha
         plp
         rep     #$80
-        bpl     L105F
+        bpl     L1050
 
         .byte   $00
         .byte   $00
 
-L105F   sep     #$80
-        bpl     _L1065
-        bmi     _L1067
+L1050   sep     #$80
+        bpl     _L1056
+        bmi     _L1058
 
-_L1065  .byte   $00
+_L1056  .byte   $00
         .byte   $00
 
-_L1067  rep     #$40
-        bvc     _L106D
+_L1058  rep     #$40
+        bvc     _L105E
 
         .byte   $00
         .byte   $00
 
-_L106D  sep     #$40
-        bvs     _L1073
+_L105E  sep     #$40
+        bvs     _L1064
 
         .byte   $00
         .byte   $00
 
-_L1073  rep     #$01
-        bcc     _L1079
+_L1064  rep     #$01
+        bcc     _L106A
 
         .byte   $00
         .byte   $00
 
-_L1079  sep     #$01
-        bcs     _L107F
+_L106A  sep     #$01
+        bcs     _L1070
 
         .byte   $00
         .byte   $00
 
-_L107F  rep     #$02
-        bne     _L1085
+_L1070  rep     #$02
+        bne     _L1076
 
         .byte   $00
         .byte   $00
 
-_L1085  sep     #$02
-        beq     _L108B
+_L1076  sep     #$02
+        beq     _L107C
 
         .byte   $00
         .byte   $00
 
-_L108B  sep     #$ff
-        lda     #$01
-        bne     _L1093
-
-        .byte   $00
-        .byte   $db
-
-_L1093  lda     #$00
-        beq     _L1099
-
-        .byte   $00
-        .byte   $db
-
-_L1099  bpl     _L109D
-
-        .byte   $00
-        .byte   $db
-
-_L109D  lda     #$80
-        bmi     _L10A3
-
-        .byte   $00
-        .byte   $db
-
-_L10A3  lda     #$ff
-        and     #$00
-        beq     _L10AB
-
-        .byte   $00
-        .byte   $db
-
-_L10AB  lda     #$00
-        ldx     #$80
-        and     #$ff
-        beq     _L10B5
-        bne     _L10B5
-
-_L10B5  lda     #$ff
-        ldx     #$00
-        and     #$7f
-        beq     _L10BF
-        bne     _L10BF
-
-_L10BF  bpl     _L10C3
-
-        .byte   $00
-        .byte   $db
-
-_L10C3  lda     #$ff
-        and     #$80
-        bmi     _L10CB
-        brk
-
-        .byte   $db
-
-_L10CB  lda     #$00
-        ldx     #$80
-        bne     _L10D3
-
-        .byte   $00
-        .byte   $db
-
-_L10D3  ora     #$00
-        beq     _L10D9
-        bne     _L10D9
-
-_L10D9  ora     #$01
-        bne     _L10DF
-
-        .byte   $00
-        .byte   $db
-
-_L10DF  lda     #$00
-        ldx     #$80
-        bmi     _L10E7
-
-        .byte   $00
-        .byte   $db
-
-_L10E7  ora     #$7f
-        bpl     _L10EF
-        bmi     _L10EF
-
-        .byte   $00
-        .byte   $db
-
-_L10EF  ora     #$80
-        bmi     _L10F5
-
-        .byte   $00
-        .byte   $db
-
-_L10F5  lda     _L10F5
-        sec
-        ror     a
-        bmi     _L10FE
-
-        .byte   $00
-        .byte   $dc
-
-_L10FE  clc
-        ror     a
-        bpl     _L1104
-
-        .byte   $00
-        .byte   $dc
-
-_L1104  lda     #$00
-        sec
-        rol     a
-        bne     _L110C
-
-        .byte   $00
-        .byte   $dc
-
-_L110C  lda     #$ff
-        lsr     a
-        bpl     _L1113
-
-        .byte   $00
-        .byte   $dd
-
-_L1113  clc
+_L107C  rep     #$20
+        .al
         php
-        sec
         plp
-        bcc     _L111B
-        brk
-
-        .byte   $00
-
-_L111B  sec
-        bcs     _L111F
-
-_L111E  clc
-_L111F  lda     $33
-        beq     _L111E
-        bcs     _L1127
-        lda     $44
-_L1127  nop
+        lda     #$1234
+        sep     #$20
+        .as
+        php
+        plp
+        lda     #$12
         rep     #$20
         .al
         sep     #$10
-        jsr     _L1143
+        jsr     _L10A6
         rep     #$30
         .xl
-        jsr     _L1149
+        jsr     _L10AC
         sep     #$30
         .as
         .xs
-        jsr     _L1149
+        jsr     _L10AC
         rep     #$20
         .al
         sep     #$10
-        jsr     _L1143
+        jsr     _L10A6
         sep     #$30
         .as
-        rts
+        jmp     _L10B3
 
         .al
-_L1143  lda     #$1234
+_L10A6  lda     #$1234
         ldx     #$ff
         rts
 
         .as
-_L1149  lda     #$ff
+_L10AC  lda     #$ff
         ldx     #$ee
         ldy     #$dd
         rts
 
+_L10B3  rts
+
diff --git a/SourceGen/SGTestData/Expected/10032-flags-and-branches_acme.S b/SourceGen/SGTestData/Expected/10032-flags-and-branches_acme.S
index b253b27..e69f405 100644
--- a/SourceGen/SGTestData/Expected/10032-flags-and-branches_acme.S
+++ b/SourceGen/SGTestData/Expected/10032-flags-and-branches_acme.S
@@ -5,17 +5,6 @@
         clc
         xce
         sep     #$ff
-        clv
-        cld
-        cli
-        clc
-        lda     #$80
-        lda     #$01
-        sed
-        sei
-        sec
-        lda     #$ff
-        adc     #$00
         sep     #$ff
         rep     #$80
         rep     #$40
@@ -65,221 +54,93 @@
         pha
         plp
         rep     #$80
-        bpl     L105F
+        bpl     L1050
 
         !byte   $00
         !byte   $00
 
-L105F   sep     #$80
-        bpl     @L1065
-        bmi     @L1067
+L1050   sep     #$80
+        bpl     @L1056
+        bmi     @L1058
 
-@L1065  !byte   $00
+@L1056  !byte   $00
         !byte   $00
 
-@L1067  rep     #$40
-        bvc     @L106D
+@L1058  rep     #$40
+        bvc     @L105E
 
         !byte   $00
         !byte   $00
 
-@L106D  sep     #$40
-        bvs     @L1073
+@L105E  sep     #$40
+        bvs     @L1064
 
         !byte   $00
         !byte   $00
 
-@L1073  rep     #$01
-        bcc     @L1079
+@L1064  rep     #$01
+        bcc     @L106A
 
         !byte   $00
         !byte   $00
 
-@L1079  sep     #$01
-        bcs     @L107F
+@L106A  sep     #$01
+        bcs     @L1070
 
         !byte   $00
         !byte   $00
 
-@L107F  rep     #$02
-        bne     @L1085
+@L1070  rep     #$02
+        bne     @L1076
 
         !byte   $00
         !byte   $00
 
-@L1085  sep     #$02
-        beq     @L108B
+@L1076  sep     #$02
+        beq     @L107C
 
         !byte   $00
         !byte   $00
 
-@L108B  sep     #$ff
-        lda     #$01
-        bne     @L1093
-
-        !byte   $00
-        !byte   $db
-
-@L1093  lda     #$00
-        beq     @L1099
-
-        !byte   $00
-        !byte   $db
-
-@L1099  bpl     @L109D
-
-        !byte   $00
-        !byte   $db
-
-@L109D  lda     #$80
-        bmi     @L10A3
-
-        !byte   $00
-        !byte   $db
-
-@L10A3  lda     #$ff
-        and     #$00
-        beq     @L10AB
-
-        !byte   $00
-        !byte   $db
-
-@L10AB  lda     #$00
-        ldx     #$80
-        and     #$ff
-        beq     @L10B5
-        bne     @L10B5
-
-@L10B5  lda     #$ff
-        ldx     #$00
-        and     #$7f
-        beq     @L10BF
-        bne     @L10BF
-
-@L10BF  bpl     @L10C3
-
-        !byte   $00
-        !byte   $db
-
-@L10C3  lda     #$ff
-        and     #$80
-        bmi     @L10CB
-        brk
-
-        !byte   $db
-
-@L10CB  lda     #$00
-        ldx     #$80
-        bne     @L10D3
-
-        !byte   $00
-        !byte   $db
-
-@L10D3  ora     #$00
-        beq     @L10D9
-        bne     @L10D9
-
-@L10D9  ora     #$01
-        bne     @L10DF
-
-        !byte   $00
-        !byte   $db
-
-@L10DF  lda     #$00
-        ldx     #$80
-        bmi     @L10E7
-
-        !byte   $00
-        !byte   $db
-
-@L10E7  ora     #$7f
-        bpl     @L10EF
-        bmi     @L10EF
-
-        !byte   $00
-        !byte   $db
-
-@L10EF  ora     #$80
-        bmi     @L10F5
-
-        !byte   $00
-        !byte   $db
-
-@L10F5  lda     @L10F5
-        sec
-        ror
-        bmi     @L10FE
-
-        !byte   $00
-        !byte   $dc
-
-@L10FE  clc
-        ror
-        bpl     @L1104
-
-        !byte   $00
-        !byte   $dc
-
-@L1104  lda     #$00
-        sec
-        rol
-        bne     @L110C
-
-        !byte   $00
-        !byte   $dc
-
-@L110C  lda     #$ff
-        lsr
-        bpl     @L1113
-
-        !byte   $00
-        !byte   $dd
-
-@L1113  clc
+@L107C  rep     #$20
+        !al
         php
-        sec
         plp
-        bcc     @L111B
-        brk
-
-        !byte   $00
-
-@L111B  sec
-        bcs     @L111F
-
-@L111E  clc
-@L111F  lda     $33
-        beq     @L111E
-        bcs     @L1127
-        lda     $44
-@L1127  nop
+        lda     #$1234
+        sep     #$20
+        !as
+        php
+        plp
+        lda     #$12
         rep     #$20
         !al
         sep     #$10
-        jsr     @L1143
+        jsr     @L10A6
         rep     #$30
         !rl
-        jsr     @L1149
+        jsr     @L10AC
         sep     #$30
         !as
         !rs
-        jsr     @L1149
+        jsr     @L10AC
         rep     #$20
         !al
         sep     #$10
-        jsr     @L1143
+        jsr     @L10A6
         sep     #$30
         !as
-        rts
+        jmp     @L10B3
 
         !al
-@L1143  lda     #$1234
+@L10A6  lda     #$1234
         ldx     #$ff
         rts
 
         !as
-@L1149  lda     #$ff
+@L10AC  lda     #$ff
         ldx     #$ee
         ldy     #$dd
         rts
 
+@L10B3  rts
+
diff --git a/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.S b/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.S
index e632fcc..890bde6 100644
--- a/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.S
+++ b/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.S
@@ -6,17 +6,6 @@
          clc
          xce
          sep     #$ff
-         clv
-         cld
-         cli
-         clc
-         lda     #$80
-         lda     #$01
-         sed
-         sei
-         sec
-         lda     #$ff
-         adc     #$00
          sep     #$ff
          rep     #$80
          rep     #$40
@@ -66,221 +55,93 @@
          pha
          plp
          rep     #$80
-         bpl     L105F
+         bpl     L1050
 
          .byte   $00
          .byte   $00
 
-L105F:   sep     #$80
-         bpl     @L1065
-         bmi     @L1067
+L1050:   sep     #$80
+         bpl     @L1056
+         bmi     @L1058
 
-@L1065:  .byte   $00
+@L1056:  .byte   $00
          .byte   $00
 
-@L1067:  rep     #$40
-         bvc     @L106D
+@L1058:  rep     #$40
+         bvc     @L105E
 
          .byte   $00
          .byte   $00
 
-@L106D:  sep     #$40
-         bvs     @L1073
+@L105E:  sep     #$40
+         bvs     @L1064
 
          .byte   $00
          .byte   $00
 
-@L1073:  rep     #$01
-         bcc     @L1079
+@L1064:  rep     #$01
+         bcc     @L106A
 
          .byte   $00
          .byte   $00
 
-@L1079:  sep     #$01
-         bcs     @L107F
+@L106A:  sep     #$01
+         bcs     @L1070
 
          .byte   $00
          .byte   $00
 
-@L107F:  rep     #$02
-         bne     @L1085
+@L1070:  rep     #$02
+         bne     @L1076
 
          .byte   $00
          .byte   $00
 
-@L1085:  sep     #$02
-         beq     @L108B
+@L1076:  sep     #$02
+         beq     @L107C
 
          .byte   $00
          .byte   $00
 
-@L108B:  sep     #$ff
-         lda     #$01
-         bne     @L1093
-
-         .byte   $00
-         .byte   $db
-
-@L1093:  lda     #$00
-         beq     @L1099
-
-         .byte   $00
-         .byte   $db
-
-@L1099:  bpl     @L109D
-
-         .byte   $00
-         .byte   $db
-
-@L109D:  lda     #$80
-         bmi     @L10A3
-
-         .byte   $00
-         .byte   $db
-
-@L10A3:  lda     #$ff
-         and     #$00
-         beq     @L10AB
-
-         .byte   $00
-         .byte   $db
-
-@L10AB:  lda     #$00
-         ldx     #$80
-         and     #$ff
-         beq     @L10B5
-         bne     @L10B5
-
-@L10B5:  lda     #$ff
-         ldx     #$00
-         and     #$7f
-         beq     @L10BF
-         bne     @L10BF
-
-@L10BF:  bpl     @L10C3
-
-         .byte   $00
-         .byte   $db
-
-@L10C3:  lda     #$ff
-         and     #$80
-         bmi     @L10CB
-         brk
-
-         .byte   $db
-
-@L10CB:  lda     #$00
-         ldx     #$80
-         bne     @L10D3
-
-         .byte   $00
-         .byte   $db
-
-@L10D3:  ora     #$00
-         beq     @L10D9
-         bne     @L10D9
-
-@L10D9:  ora     #$01
-         bne     @L10DF
-
-         .byte   $00
-         .byte   $db
-
-@L10DF:  lda     #$00
-         ldx     #$80
-         bmi     @L10E7
-
-         .byte   $00
-         .byte   $db
-
-@L10E7:  ora     #$7f
-         bpl     @L10EF
-         bmi     @L10EF
-
-         .byte   $00
-         .byte   $db
-
-@L10EF:  ora     #$80
-         bmi     @L10F5
-
-         .byte   $00
-         .byte   $db
-
-@L10F5:  lda     @L10F5
-         sec
-         ror     A
-         bmi     @L10FE
-
-         .byte   $00
-         .byte   $dc
-
-@L10FE:  clc
-         ror     A
-         bpl     @L1104
-
-         .byte   $00
-         .byte   $dc
-
-@L1104:  lda     #$00
-         sec
-         rol     A
-         bne     @L110C
-
-         .byte   $00
-         .byte   $dc
-
-@L110C:  lda     #$ff
-         lsr     A
-         bpl     @L1113
-
-         .byte   $00
-         .byte   $dd
-
-@L1113:  clc
+@L107C:  rep     #$20
+         .a16
          php
-         sec
          plp
-         bcc     @L111B
-         brk
-
-         .byte   $00
-
-@L111B:  sec
-         bcs     @L111F
-
-@L111E:  clc
-@L111F:  lda     $33
-         beq     @L111E
-         bcs     @L1127
-         lda     $44
-@L1127:  nop
+         lda     #$1234
+         sep     #$20
+         .a8
+         php
+         plp
+         lda     #$12
          rep     #$20
          .a16
          sep     #$10
-         jsr     @L1143
+         jsr     @L10A6
          rep     #$30
          .i16
-         jsr     @L1149
+         jsr     @L10AC
          sep     #$30
          .a8
          .i8
-         jsr     @L1149
+         jsr     @L10AC
          rep     #$20
          .a16
          sep     #$10
-         jsr     @L1143
+         jsr     @L10A6
          sep     #$30
          .a8
-         rts
+         jmp     @L10B3
 
          .a16
-@L1143:  lda     #$1234
+@L10A6:  lda     #$1234
          ldx     #$ff
          rts
 
          .a8
-@L1149:  lda     #$ff
+@L10AC:  lda     #$ff
          ldx     #$ee
          ldy     #$dd
          rts
 
+@L10B3:  rts
+
diff --git a/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.cfg b/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.cfg
index 8fc8fe5..fd70fc3 100644
--- a/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.cfg
+++ b/SourceGen/SGTestData/Expected/10032-flags-and-branches_cc65.cfg
@@ -1,7 +1,7 @@
 # 6502bench SourceGen generated linker script for 10032-flags-and-branches
 MEMORY {
     MAIN: file=%O, start=%S, size=65536;
-#    MEM000: file=%O, start=$1000, size=336;
+#    MEM000: file=%O, start=$1000, size=180;
 }
 SEGMENTS {
     CODE: load=MAIN, type=rw;
diff --git a/SourceGen/SGTestData/Expected/10032-flags-and-branches_merlin32.S b/SourceGen/SGTestData/Expected/10032-flags-and-branches_merlin32.S
index c8c7666..5e9a873 100644
--- a/SourceGen/SGTestData/Expected/10032-flags-and-branches_merlin32.S
+++ b/SourceGen/SGTestData/Expected/10032-flags-and-branches_merlin32.S
@@ -2,17 +2,6 @@
          clc
          xce
          sep   #$ff
-         clv
-         cld
-         cli
-         clc
-         lda   #$80
-         lda   #$01
-         sed
-         sei
-         sec
-         lda   #$ff
-         adc   #$00
          sep   #$ff
          rep   #$80
          rep   #$40
@@ -60,220 +49,92 @@
          pha
          plp
          rep   #$80
-         bpl   L105F
+         bpl   L1050
 
          dfb   $00
          dfb   $00
 
-L105F    sep   #$80
-         bpl   :L1065
-         bmi   :L1067
+L1050    sep   #$80
+         bpl   :L1056
+         bmi   :L1058
 
-:L1065   dfb   $00
+:L1056   dfb   $00
          dfb   $00
 
-:L1067   rep   #$40
-         bvc   :L106D
+:L1058   rep   #$40
+         bvc   :L105E
 
          dfb   $00
          dfb   $00
 
-:L106D   sep   #$40
-         bvs   :L1073
+:L105E   sep   #$40
+         bvs   :L1064
 
          dfb   $00
          dfb   $00
 
-:L1073   rep   #$01
-         bcc   :L1079
+:L1064   rep   #$01
+         bcc   :L106A
 
          dfb   $00
          dfb   $00
 
-:L1079   sep   #$01
-         bcs   :L107F
+:L106A   sep   #$01
+         bcs   :L1070
 
          dfb   $00
          dfb   $00
 
-:L107F   rep   #$02
-         bne   :L1085
+:L1070   rep   #$02
+         bne   :L1076
 
          dfb   $00
          dfb   $00
 
-:L1085   sep   #$02
-         beq   :L108B
+:L1076   sep   #$02
+         beq   :L107C
 
          dfb   $00
          dfb   $00
 
-:L108B   sep   #$ff
-         lda   #$01
-         bne   :L1093
-
-         dfb   $00
-         dfb   $db
-
-:L1093   lda   #$00
-         beq   :L1099
-
-         dfb   $00
-         dfb   $db
-
-:L1099   bpl   :L109D
-
-         dfb   $00
-         dfb   $db
-
-:L109D   lda   #$80
-         bmi   :L10A3
-
-         dfb   $00
-         dfb   $db
-
-:L10A3   lda   #$ff
-         and   #$00
-         beq   :L10AB
-
-         dfb   $00
-         dfb   $db
-
-:L10AB   lda   #$00
-         ldx   #$80
-         and   #$ff
-         beq   :L10B5
-         bne   :L10B5
-
-:L10B5   lda   #$ff
-         ldx   #$00
-         and   #$7f
-         beq   :L10BF
-         bne   :L10BF
-
-:L10BF   bpl   :L10C3
-
-         dfb   $00
-         dfb   $db
-
-:L10C3   lda   #$ff
-         and   #$80
-         bmi   :L10CB
-         brk
-
-         dfb   $db
-
-:L10CB   lda   #$00
-         ldx   #$80
-         bne   :L10D3
-
-         dfb   $00
-         dfb   $db
-
-:L10D3   ora   #$00
-         beq   :L10D9
-         bne   :L10D9
-
-:L10D9   ora   #$01
-         bne   :L10DF
-
-         dfb   $00
-         dfb   $db
-
-:L10DF   lda   #$00
-         ldx   #$80
-         bmi   :L10E7
-
-         dfb   $00
-         dfb   $db
-
-:L10E7   ora   #$7f
-         bpl   :L10EF
-         bmi   :L10EF
-
-         dfb   $00
-         dfb   $db
-
-:L10EF   ora   #$80
-         bmi   :L10F5
-
-         dfb   $00
-         dfb   $db
-
-:L10F5   lda   :L10F5
-         sec
-         ror   A
-         bmi   :L10FE
-
-         dfb   $00
-         dfb   $dc
-
-:L10FE   clc
-         ror   A
-         bpl   :L1104
-
-         dfb   $00
-         dfb   $dc
-
-:L1104   lda   #$00
-         sec
-         rol   A
-         bne   :L110C
-
-         dfb   $00
-         dfb   $dc
-
-:L110C   lda   #$ff
-         lsr   A
-         bpl   :L1113
-
-         dfb   $00
-         dfb   $dd
-
-:L1113   clc
+:L107C   rep   #$20
+         mx    %01
          php
-         sec
          plp
-         bcc   :L111B
-         brk
-
-         dfb   $00
-
-:L111B   sec
-         bcs   :L111F
-
-:L111E   clc
-:L111F   lda   $33
-         beq   :L111E
-         bcs   :L1127
-         lda   $44
-:L1127   nop
+         lda   #$1234
+         sep   #$20
+         mx    %11
+         php
+         plp
+         lda   #$12
          rep   #$20
          mx    %01
          sep   #$10
-         jsr   :L1143
+         jsr   :L10A6
          rep   #$30
          mx    %00
-         jsr   :L1149
+         jsr   :L10AC
          sep   #$30
          mx    %11
-         jsr   :L1149
+         jsr   :L10AC
          rep   #$20
          mx    %01
          sep   #$10
-         jsr   :L1143
+         jsr   :L10A6
          sep   #$30
          mx    %11
-         rts
+         jmp   :L10B3
 
          mx    %01
-:L1143   lda   #$1234
+:L10A6   lda   #$1234
          ldx   #$ff
          rts
 
          mx    %11
-:L1149   lda   #$ff
+:L10AC   lda   #$ff
          ldx   #$ee
          ldy   #$dd
          rts
 
+:L10B3   rts
+
diff --git a/SourceGen/SGTestData/Source/10020-embedded-instructions.S b/SourceGen/SGTestData/Source/10020-embedded-instructions.S
new file mode 100644
index 0000000..4e1a0cf
--- /dev/null
+++ b/SourceGen/SGTestData/Source/10020-embedded-instructions.S
@@ -0,0 +1,80 @@
+; Copyright 2018 faddenSoft. All Rights Reserved.
+; See the LICENSE.txt file for distribution terms (Apache 2.0).
+;
+; Assembler: Merlin 32
+; 6502 version
+
+        org     $1000
+
+        jsr     test1
+        jsr     test3
+        jsr     test4
+        jsr     test5
+        jmp     test6
+
+; TEST #1: simple example
+test1   lda     #$00
+        dfb     $2c         ;BIT abs
+:inner  lda     #$01
+        beq     :inner
+        rts
+
+; TEST #3: embedded with non-instruction byte
+;
+; The code analyzer sees two paths, involving the three bytes.
+; The first is the three-byte JSR, the second is the one-byte
+; RTS.  The third NOP byte is never "executed" by the analyzer,
+; but because of the way we display embedded instructions it
+; gets put on its own line.  Since it's not an instruction start
+; or a data item, things get confused.  (This is referred to as
+; an "embedded orphan" in the code.)
+
+test3   dfb     $20         ;JSR
+:mid    dfb     $60         ;RTS
+        dfb     $ea         ;NOP
+        bvs     :mid
+
+
+; TEST #4: overlapping chain
+;
+; Each BIT instruction is three bytes, and each byte is a branch target,
+; so we get a string of embedded instructions.
+test4
+:bits   hex     2c2c2c2c2c2c2c2c2ceaea
+        asl
+        bcc     :bits
+        asl
+        bcc     :bits+1
+        asl
+        bcc     :bits+2
+        asl
+        bcc     :bits+3
+        asl
+        bcc     :bits+4
+        asl
+        bcc     :bits+5
+        asl
+        bcc     :bits+6
+        asl
+        bcc     :bits+7
+        asl
+        bcc     :bits+8
+        asl
+        bcc     :bits+9
+        rts
+
+; TEST #5: another overlap
+;
+; Trying to be a little different.
+test5   dfb     $2c
+:mid1   nop
+        hex     ad
+:mid2   lda     $00
+        asl
+        bcc     :mid1
+        asl
+        bcc     :mid2
+
+; TEST #6: "embedded" off the end of the file
+test6
+        dfb     $ad         ;lda
diff --git a/SourceGen/SGTestData/Source/10022-embedded-instructions.S b/SourceGen/SGTestData/Source/10022-embedded-instructions.S
index 71c596a..39805ae 100644
--- a/SourceGen/SGTestData/Source/10022-embedded-instructions.S
+++ b/SourceGen/SGTestData/Source/10022-embedded-instructions.S
@@ -2,28 +2,12 @@
 ; See the LICENSE.txt file for distribution terms (Apache 2.0).
 ;
 ; Assembler: Merlin 32
+; 65816 version
 
         org     $1000
 
-; 65816 mode with short regs
-        clc
-        xce
-        sep     #$30
-        mx      %11
-
-        jsr     test1
         jsr     test2
-        jsr     test3
-        jsr     test4
-        jsr     test5
-        rts
-
-; TEST #1: simple example
-test1   lda     #$00
-        dfb     $2c         ;BIT abs
-:inner  lda     #$01
-        beq     :inner
-        rts
+        jmp     test6
 
 ; TEST #2: embedded with break path
 ;
@@ -40,71 +24,24 @@ test1   lda     #$00
 ;
 ; This is different from the typical embedded instruction,
 ; where the inner is contained entirely within the outer.
+;
+; (Not sure this is interesting anymore with default 1-byte BRK.)
 test2   sep     #$30        ;short regs
         mx      %00         ;pretend they're long
 
         lda     $00         ;load something to scramble flags
-        beq     :store
+        beq     :store1
         lda     #$0000
-:store  stal    $012345
+:store1 stal    $012345
+
+; Try it a different way.  This creates two streams of execution.
+        lda     $00
+        beq     :store2
+        lda     #$8500
+:store2 stal    $012345
+        nop
         rts
 
-; TEST #3: embedded with non-instruction byte
-;
-; The code analyzer sees two paths, involving the three bytes.
-; The first is the three-byte JSR, the second is the one-byte
-; RTS.  The third NOP byte is never "executed" by the analyzer,
-; but because of the way we display embedded instructions it
-; gets put on its own line.  Since it's not an instruction start
-; or a data item, things get confused.  (This is referred to as
-; an "embedded orphan" in the code.)
-
-test3   dfb     $20         ;JSR
-:mid    dfb     $60         ;RTS
-        dfb     $ea         ;NOP
-        bra     :mid
-
-
-; TEST #4: overlapping chain
-;
-; Each BIT instruction is three bytes, and each byte is a branch target,
-; so we get a string of embedded instructions.
-test4
-:bits   hex     2c2c2c2c2c2c2c2c2ceaea
-        asl
-        bcc     :bits
-        asl
-        bcc     :bits+1
-        asl
-        bcc     :bits+2
-        asl
-        bcc     :bits+3
-        asl
-        bcc     :bits+4
-        asl
-        bcc     :bits+5
-        asl
-        bcc     :bits+6
-        asl
-        bcc     :bits+7
-        asl
-        bcc     :bits+8
-        asl
-        bcc     :bits+9
-        rts
-
-; TEST #5: another overlap
-;
-; Trying to be a little different.
-test5   dfb     $2c
-:mid1   nop
-        hex     ad
-:mid2   lda     $00
-        asl
-        bcc     :mid1
-        asl
-        bcc     :mid2
-
 ; TEST #6: "embedded" off the end of the file
+test6
         dfb     $af         ;ldal
-
diff --git a/SourceGen/SGTestData/Source/10030-flags-and-branches.S b/SourceGen/SGTestData/Source/10030-flags-and-branches.S
new file mode 100644
index 0000000..a44514b
--- /dev/null
+++ b/SourceGen/SGTestData/Source/10030-flags-and-branches.S
@@ -0,0 +1,164 @@
+; Copyright 2018 faddenSoft. All Rights Reserved.
+; See the LICENSE.txt file for distribution terms (Apache 2.0).
+;
+; Assembler: Merlin 32
+; 6502 version
+
+        org     $1000
+
+; clear individual flags with instructions
+; (this has no effect on the assembled output, but you can see the
+; effects on the "status" column in the display list)
+        clv
+        cld
+        cli
+        clc
+        lda     #$80        ;clear Z
+        lda     #$01        ;clear N
+
+        sed
+        sei
+        sec
+        lda     #$ff        ;set N
+        adc     #$00        ;set V, Z (actually scrambles NVZC)
+
+; check branch instructions as best we can; NVMXDIZC
+        lda     #$00
+        pha
+        plp                 ;without a nearby PHP, flags will be scrambled
+
+ok_bmi  clv
+        bvc     ok_bvc
+        bvs     ok_bvs
+        brk     $00
+
+ok_bvc
+ok_bvs  clc
+        bcc     ok_bcc
+        brk     $00
+
+ok_bcc  sec
+        bcs     ok_bcs
+        brk     $00
+ok_bcs
+
+; check NZ flags set by immediate load
+        lda     #$01
+        bne     ok_nzero
+        brk     $db
+ok_nzero
+        lda     #$00
+        beq     ok_zero
+        brk     $db
+ok_zero
+        bpl     ok_pos
+        brk     $db
+ok_pos
+        lda     #$80
+        bmi     ok_neg
+        brk     $db
+ok_neg
+
+; check NZ flags set by immediate AND; only $00 / <=$7f have meaning
+        lda     #$ff
+        and     #$00
+        beq     ok_andZ1
+        brk     $db
+ok_andZ1
+        lda     #$00
+        ldx     #$80
+        and     #$ff
+        beq     ok_andZ1A
+        bne     ok_andZ1A
+ok_andZ1A
+        lda     #$ff
+        ldx     #$00
+        and     #$7f
+        beq     ok_andZ0
+        bne     ok_andZ0
+ok_andZ0
+        bpl     ok_andN0
+        brk     $db
+ok_andN0
+        lda     #$ff
+        and     #$80
+        bpl     ok_andN1
+        bmi     ok_andN1
+        brk     $db
+ok_andN1
+
+; check NZ flags set by immediate ORA; only nonzero / >=$80 have meaning
+        lda     #$00
+        ldx     #$80
+        bne     :next1
+        brk     $db
+:next1  ora     #$00        ;can't know what A-reg holds, so Z=indeterminate
+        beq     ok_oraZ1
+        bne     ok_oraZ1
+ok_oraZ1
+        ora     #$01
+        bne     ok_oraZ0
+        brk     $db
+ok_oraZ0
+        lda     #$00
+        ldx     #$80
+        bmi     :next2
+        brk     $db
+:next2  ora     #$7f        ;N-flag clear, but analyzer doesn't know,
+        bpl     ok_oraN0    ; so both of these are considered viable
+        bmi     ok_oraN0
+        brk     $db
+ok_oraN0
+        ora     #$80
+        bmi     ok_oraN1
+        brk     $db
+ok_oraN1
+
+; check rol/ror
+:foo    lda     :foo        ;scramble N/V
+        sec
+        ror     A           ;rotates the carry into the hi bit (N)
+        bmi     ok_ror1
+        brk     $dc
+ok_ror1
+        clc
+        ror     A           ;now try with carry clear
+        bpl     ok_ror2
+        brk     $dc
+ok_ror2
+        lda     #$00        ;set Z=1
+        sec
+        rol     A           ;set Z=0 (could also set C=0)
+        bne     ok_rol1
+        brk     $dc
+ok_rol1
+
+; check lsr
+        lda     #$ff
+        lsr     A           ;lsr always clears the high bit
+        bpl     ok_lsr
+        brk     $dd
+ok_lsr
+
+; simple "smart" plp test, changes state according to default
+        clc
+        php
+        sec
+        plp                 ;"smart" restores carry
+        bcc     ok_plp      ; and makes this a branch-always
+        nop                 ;non-smart is indeterminate
+ok_plp
+
+; regression test for bug in analyzer
+        sec                 ;here carry is clear
+        bcs     flg2
+flg1    clc
+
+flg2    lda     $33
+        beq     flg1
+        bcs     flg3        ;this should NOT be branch-always
+        lda     $44
+flg3    nop
+
+done
+        rts
diff --git a/SourceGen/SGTestData/Source/10032-flags-and-branches.S b/SourceGen/SGTestData/Source/10032-flags-and-branches.S
index 7449c81..133d5d5 100644
--- a/SourceGen/SGTestData/Source/10032-flags-and-branches.S
+++ b/SourceGen/SGTestData/Source/10032-flags-and-branches.S
@@ -2,6 +2,7 @@
 ; See the LICENSE.txt file for distribution terms (Apache 2.0).
 ;
 ; Assembler: Merlin 32
+; 65816 version
 
         org     $1000
         clc
@@ -9,22 +10,6 @@
         sep     #$ff        ;set all flags
         mx      %11
 
-; clear individual flags with instructions
-; (this has no effect on the assembled output, but you can see the
-; effects on the "status" column in the display list)
-        clv
-        cld
-        cli
-        clc
-        lda     #$80        ;clear Z
-        lda     #$01        ;clear N
-
-        sed
-        sei
-        sec
-        lda     #$ff        ;set N
-        adc     #$00        ;set V, Z (actually scrambles NVZC)
-
 ; clear individual flags with REP
         sep     #$ff
         rep     #$80
@@ -112,126 +97,20 @@ ok_bne  sep     #$02
 
 ok_beq
 
-; check NZ flags set by immediate load
-        sep     #$ff        ;set all
-        mx      %11
-        lda     #$01
-        bne     ok_nzero
-        brk     $db
-ok_nzero
-        lda     #$00
-        beq     ok_zero
-        brk     $db
-ok_zero
-        bpl     ok_pos
-        brk     $db
-ok_pos
-        lda     #$80
-        bmi     ok_neg
-        brk     $db
-ok_neg
 
-; check NZ flags set by immediate AND
-        lda     #$ff
-        and     #$00
-        beq     ok_andZ1
-        brk     $db
-ok_andZ1
-        lda     #$00
-        ldx     #$80
-        and     #$ff
-        beq     ok_andZ1A
-        bne     ok_andZ1A
-ok_andZ1A
-        lda     #$ff
-        ldx     #$00
-        and     #$7f
-        beq     ok_andZ0
-        bne     ok_andZ0
-ok_andZ0
-        bpl     ok_andN0
-        brk     $db
-ok_andN0
-        lda     #$ff
-        and     #$80
-        bmi     ok_andN1
-        brk     $db
-ok_andN1
-
-; check NZ flags set by immediate ORA
-        lda     #$00
-        ldx     #$80
-        bne     :next1
-        brk     $db
-:next1  ora     #$00
-        beq     ok_oraZ1
-        bne     ok_oraZ1
-ok_oraZ1
-        ora     #$01
-        bne     ok_oraZ0
-        brk     $db
-ok_oraZ0
-        lda     #$00
-        ldx     #$80
-        bmi     :next2
-        brk     $db
-:next2  ora     #$7f        ;N-flag clear, but analyzer doesn't know
-        bpl     ok_oraN0    ;so both of these are considered viable
-        bmi     ok_oraN0
-        brk     $db
-ok_oraN0
-        ora     #$80
-        bmi     ok_oraN1
-        brk     $db
-ok_oraN1
-
-; check rol/ror
-:foo    lda     :foo        ;scramble N/V
-        sec
-        ror     A           ;rotates the carry into the hi bit (N)
-        bmi     ok_ror1
-        brk     $dc
-ok_ror1
-        clc
-        ror     A           ;now try with carry clear
-        bpl     ok_ror2
-        brk     $dc
-ok_ror2
-        lda     #$00        ;set Z=1
-        sec
-        rol     A           ;set Z=0 (could also set C=0)
-        bne     ok_rol1
-        brk     $dc
-ok_rol1
-
-; check lsr
-        lda     #$ff
-        lsr     A           ;lsr always clears the high bit
-        bpl     ok_lsr
-        brk     $dd
-ok_lsr
-
-; simple php/plp pair test
-        clc
+; Test M/X behavior across PHP/PLP.  The flags should be left alone
+; (non-smart mode), or set to whatever they were on the previous PHP
+; (smart mode).
+        rep     #$20
         php
-        sec
         plp                 ;should restore cleared carry
-        bcc     ok_plp
-        brk     $00
-ok_plp
+        lda     #$1234
+        sep     #$20
+        php
+        plp
+        lda     #$12
 
-; regression test for bug in analyzer
-        sec                 ;here carry is clear
-        bcs     flg2
-flg1    clc
-
-flg2    lda     $33
-        beq     flg1
-        bcs     flg3        ;this should NOT be branch-always
-        lda     $44
-flg3    nop
-
-; test tracking across subroutine calls
+; test tracking M/X across subroutine calls
         rep     #$20        ;long a
         sep     #$10        ;short x/y
         mx      %01
@@ -254,7 +133,7 @@ flg3    nop
 ; leave the main routine with short flags set
         sep     #$30
         mx      %11
-        rts
+        jmp     done
 
 
 ; only called with longm/shortx
@@ -272,3 +151,5 @@ ambig_subr
         ldy     #$dd
         rts
 
+done
+        rts