diff --git a/Asm65/CpuDef.cs b/Asm65/CpuDef.cs index 64937af..907d8d1 100644 --- a/Asm65/CpuDef.cs +++ b/Asm65/CpuDef.cs @@ -242,7 +242,8 @@ namespace Asm65 { /// Cycle count. public int GetCycles(int opNum, StatusFlags flags, OpDef.BranchTaken branchTaken, bool branchCrossesPage) { - // The irrelevant modifiers have already been stripped out. + // The irrelevant modifiers have already been stripped out, e.g. OneIfD1 only + // affects the 65C02. OpDef.CycleMod mods = mCycleMods[opNum]; int cycles = mCycleCounts[opNum]; diff --git a/SourceGen/SGTestData/2020-cycle-counts b/SourceGen/SGTestData/2020-cycle-counts new file mode 100644 index 0000000..a35ec67 Binary files /dev/null and b/SourceGen/SGTestData/2020-cycle-counts differ diff --git a/SourceGen/SGTestData/2020-cycle-counts.dis65 b/SourceGen/SGTestData/2020-cycle-counts.dis65 new file mode 100644 index 0000000..c53e343 --- /dev/null +++ b/SourceGen/SGTestData/2020-cycle-counts.dis65 @@ -0,0 +1,27 @@ +### 6502bench SourceGen dis65 v1.0 ### +{ +"_ContentVersion":2,"FileDataLength":126,"FileDataCrc32":1805483931,"ProjectProps":{ +"CpuName":"65816","IncludeUndocumentedInstr":false,"EntryFlags":32702671,"AutoLabelStyle":"Simple","AnalysisParams":{ +"AnalyzeUncategorizedData":true,"DefaultTextScanMode":"LowHighAscii","MinCharsForString":4,"SeekNearbyTargets":true,"SmartPlpHandling":true}, +"PlatformSymbolFileIdentifiers":[],"ExtensionScriptFileIdentifiers":[],"ProjectSyms":{ +"__ENABLE_CYCLE_COUNTS":{ +"DataDescriptor":{ +"Length":1,"Format":"NumericLE","SubFormat":"Decimal","SymbolRef":null}, +"Comment":"","Label":"__ENABLE_CYCLE_COUNTS","Value":1,"Source":"Project","Type":"Constant"}}}, +"AddressMap":[{ +"Offset":0,"Addr":4336}],"TypeHints":[{ +"Low":0,"High":0,"Hint":"Code"}],"StatusFlagOverrides":{ +}, +"Comments":{ +}, +"LongComments":{ +"-2147483647":{ +"Text":"6502bench SourceGen v1.3.0-dev6","BoxMode":false,"MaxWidth":80,"BackgroundColor":0}}, +"Notes":{ +}, +"UserLabels":{ +}, +"OperandFormats":{ +}, +"LvTables":{ +}} diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts_64tass.S b/SourceGen/SGTestData/Expected/2020-cycle-counts_64tass.S new file mode 100644 index 0000000..a0616a5 --- /dev/null +++ b/SourceGen/SGTestData/Expected/2020-cycle-counts_64tass.S @@ -0,0 +1,80 @@ +;6502bench SourceGen v1.3.0-dev6 + .cpu "65816" +* = $10f0 + .as + .xs +L10F0 sec ;2 + xce ;2 + bra L1108 ;4 + + .fill 20,$00 + +L1108 bra L110A ;3 + +L110A lda #$00 ;2 + beq L1110 ;3 + + .byte $00 + .byte $00 + +L1110 bne L1110 ;2 + lda $1234 ;4 + beq L1119 ;2+ + brk ;7 + + .byte $01 + +L1119 lda $22,s ;4 + trb $02 ;5+ + asl $03,x ;6+ + clc ;2 + xce ;2 + rep #$30 ;3 + .al + .xl + lda #$0011 ;3 + ldy #$0022 ;3 + trb $04 ;7+ + asl $05,x ;8+ + ldx $1235 ;5 + beq L1134 ;2+ + brk ;8 + + .byte $02 + +L1134 lda $33,s ;5 + beq L113A ;2+ + bra L10F0 ;3 + +L113A rep #$20 ;3 + sep #$10 ;3 + .xs + sta $10 ;4+ + stx $11 ;3+ + sty $12 ;3+ + rep #$10 ;3 + .xl + sep #$20 ;3 + .as + sta $11 ;3+ + stx $12 ;4+ + sty $13 ;4+ + rep #$30 ;3 + .al + lda $1234 ;5 + adc #$0066 ;3 + adc $1235 ;5 + sed ;2 + adc #$0077 ;3 + adc $1236 ;5 + sec ;2 + xce ;2 + .as + .xs + sbc #$88 ;2 + sbc $1237 ;4 + cld ;2 + sbc #$99 ;2 + sbc $1238 ;4 + rts ;6 + diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts_Merlin32.S b/SourceGen/SGTestData/Expected/2020-cycle-counts_Merlin32.S new file mode 100644 index 0000000..3b410db --- /dev/null +++ b/SourceGen/SGTestData/Expected/2020-cycle-counts_Merlin32.S @@ -0,0 +1,75 @@ +;6502bench SourceGen v1.3.0-dev6 + org $10f0 +L10F0 sec ;2 + xce ;2 + bra L1108 ;4 + + ds 20,$00 + +L1108 bra L110A ;3 + +L110A lda #$00 ;2 + beq L1110 ;3 + + dfb $00 + dfb $00 + +L1110 bne L1110 ;2 + lda $1234 ;4 + beq L1119 ;2+ + brk ;7 + + dfb $01 + +L1119 lda $22,S ;4 + trb $02 ;5+ + asl $03,x ;6+ + clc ;2 + xce ;2 + rep #$30 ;3 + mx %00 + lda #$0011 ;3 + ldy #$0022 ;3 + trb $04 ;7+ + asl $05,x ;8+ + ldx $1235 ;5 + beq L1134 ;2+ + brk ;8 + + dfb $02 + +L1134 lda $33,S ;5 + beq L113A ;2+ + bra L10F0 ;3 + +L113A rep #$20 ;3 + sep #$10 ;3 + mx %01 + sta $10 ;4+ + stx $11 ;3+ + sty $12 ;3+ + rep #$10 ;3 + mx %00 + sep #$20 ;3 + mx %10 + sta $11 ;3+ + stx $12 ;4+ + sty $13 ;4+ + rep #$30 ;3 + mx %00 + lda $1234 ;5 + adc #$0066 ;3 + adc $1235 ;5 + sed ;2 + adc #$0077 ;3 + adc $1236 ;5 + sec ;2 + xce ;2 + mx %11 + sbc #$88 ;2 + sbc $1237 ;4 + cld ;2 + sbc #$99 ;2 + sbc $1238 ;4 + rts ;6 + diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts_acme.S b/SourceGen/SGTestData/Expected/2020-cycle-counts_acme.S new file mode 100644 index 0000000..b288b2c --- /dev/null +++ b/SourceGen/SGTestData/Expected/2020-cycle-counts_acme.S @@ -0,0 +1,80 @@ +;6502bench SourceGen v1.3.0-dev6 + !cpu 65816 +* = $10f0 + !as + !rs +L10F0 sec ;2 + xce ;2 + bra L1108 ;4 + + !fill 20,$00 + +L1108 bra L110A ;3 + +L110A lda #$00 ;2 + beq L1110 ;3 + + !byte $00 + !byte $00 + +L1110 bne L1110 ;2 + lda $1234 ;4 + beq L1119 ;2+ + brk ;7 + + !byte $01 + +L1119 lda $22,S ;4 + trb $02 ;5+ + asl $03,x ;6+ + clc ;2 + xce ;2 + rep #$30 ;3 + !al + !rl + lda #$0011 ;3 + ldy #$0022 ;3 + trb $04 ;7+ + asl $05,x ;8+ + ldx $1235 ;5 + beq L1134 ;2+ + brk ;8 + + !byte $02 + +L1134 lda $33,S ;5 + beq L113A ;2+ + bra L10F0 ;3 + +L113A rep #$20 ;3 + sep #$10 ;3 + !rs + sta $10 ;4+ + stx $11 ;3+ + sty $12 ;3+ + rep #$10 ;3 + !rl + sep #$20 ;3 + !as + sta $11 ;3+ + stx $12 ;4+ + sty $13 ;4+ + rep #$30 ;3 + !al + lda $1234 ;5 + adc #$0066 ;3 + adc $1235 ;5 + sed ;2 + adc #$0077 ;3 + adc $1236 ;5 + sec ;2 + xce ;2 + !as + !rs + sbc #$88 ;2 + sbc $1237 ;4 + cld ;2 + sbc #$99 ;2 + sbc $1238 ;4 + rts ;6 + diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.S b/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.S new file mode 100644 index 0000000..f8b865d --- /dev/null +++ b/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.S @@ -0,0 +1,81 @@ +;6502bench SourceGen v1.3.0-dev6 + .setcpu "65816" +; .segment "SEG000" + .org $10f0 + .a8 + .i8 +L10F0: sec ;2 + xce ;2 + bra L1108 ;4 + + .res 20,$00 + +L1108: bra L110A ;3 + +L110A: lda #$00 ;2 + beq L1110 ;3 + + .byte $00 + .byte $00 + +L1110: bne L1110 ;2 + lda $1234 ;4 + beq L1119 ;2+ + brk ;7 + + .byte $01 + +L1119: lda $22,S ;4 + trb $02 ;5+ + asl $03,x ;6+ + clc ;2 + xce ;2 + rep #$30 ;3 + .a16 + .i16 + lda #$0011 ;3 + ldy #$0022 ;3 + trb $04 ;7+ + asl $05,x ;8+ + ldx $1235 ;5 + beq L1134 ;2+ + brk ;8 + + .byte $02 + +L1134: lda $33,S ;5 + beq L113A ;2+ + bra L10F0 ;3 + +L113A: rep #$20 ;3 + sep #$10 ;3 + .i8 + sta $10 ;4+ + stx $11 ;3+ + sty $12 ;3+ + rep #$10 ;3 + .i16 + sep #$20 ;3 + .a8 + sta $11 ;3+ + stx $12 ;4+ + sty $13 ;4+ + rep #$30 ;3 + .a16 + lda $1234 ;5 + adc #$0066 ;3 + adc $1235 ;5 + sed ;2 + adc #$0077 ;3 + adc $1236 ;5 + sec ;2 + xce ;2 + .a8 + .i8 + sbc #$88 ;2 + sbc $1237 ;4 + cld ;2 + sbc #$99 ;2 + sbc $1238 ;4 + rts ;6 + diff --git a/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.cfg b/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.cfg new file mode 100644 index 0000000..cda17f9 --- /dev/null +++ b/SourceGen/SGTestData/Expected/2020-cycle-counts_cc65.cfg @@ -0,0 +1,11 @@ +# 6502bench SourceGen generated linker script for 2020-cycle-counts +MEMORY { + MAIN: file=%O, start=%S, size=65536; +# MEM000: file=%O, start=$10f0, size=126; +} +SEGMENTS { + CODE: load=MAIN, type=rw; +# SEG000: load=MEM000, type=rw; +} +FEATURES {} +SYMBOLS {} diff --git a/SourceGen/SGTestData/Source/2020-cycle-counts.S b/SourceGen/SGTestData/Source/2020-cycle-counts.S new file mode 100644 index 0000000..f7691db --- /dev/null +++ b/SourceGen/SGTestData/Source/2020-cycle-counts.S @@ -0,0 +1,80 @@ +; Copyright 2019 faddenSoft. All Rights Reserved. +; See the LICENSE.txt file for distribution terms (Apache 2.0). +; +; Assembler: Merlin 32 + +; Exercise cycle counting. We use 65816 to test the behavior with variable- +; width registers. This means we're not testing the 65C02 D-flag behavior +; or some other non-65816 quirks. If that becomes an issue we'll need to +; create additional tests. +; +; Very little editing required. Just set the initial ORG and add +; "__ENABLE_CYCLE_COUNTS" to the list of project symbols. + + org $10f0 +start sec + xce + mx %11 + bra cont ;crosses page boundary + ds 20 + +cont bra near +near + + lda #$00 + beq next ;always (3 cycles) + brk $00 +next bne next ;never (2 cycles) + lda $1234 + beq maybe ;sometimes (2+ cycles) + brk $01 ;(7 cycles) +maybe lda $22,S + trb $02 + asl $03,x + + clc + xce + rep #$30 + mx %00 + + lda #$11 + ldy #$22 + trb $04 ;should be +2 cycles + asl $05,x ;should be +2 cycles + ldx $1235 + beq maybe2 + brk $02 ;(8 cycles) +maybe2 lda $33,S + beq maybe3 + bra start ;crosses page boundary, no + when E=0 +maybe3 + + rep #$20 + sep #$10 + sta $10 + stx $11 + sty $12 + rep #$10 + sep #$20 + sta $11 + stx $12 + sty $13 + rep #$30 + +; On the 65816, the setting of the decimal flag should NOT have any effect. + lda $1234 + adc #$66 + adc $1235 + sed + adc #$77 + adc $1236 + + sec + xce + sbc #$88 + sbc $1237 + cld + sbc #$99 + sbc $1238 + rts + diff --git a/SourceGen/Tests/GenTest.cs b/SourceGen/Tests/GenTest.cs index f9413d4..f7f8737 100644 --- a/SourceGen/Tests/GenTest.cs +++ b/SourceGen/Tests/GenTest.cs @@ -422,6 +422,7 @@ namespace SourceGen.Tests { // desired value. Easier to just have a set of named features. const string ENABLE_LABEL_LOCALIZATION = "__ENABLE_LABEL_LOCALIZATION"; const string ENABLE_LABEL_NEWLINE = "__ENABLE_LABEL_NEWLINE"; + const string ENABLE_CYCLE_COUNTS = "__ENABLE_CYCLE_COUNTS"; if (project.ProjectProps.ProjectSyms.ContainsKey(ENABLE_LABEL_LOCALIZATION)) { settings.SetBool(AppSettings.SRCGEN_DISABLE_LABEL_LOCALIZATION, false); @@ -429,6 +430,9 @@ namespace SourceGen.Tests { if (project.ProjectProps.ProjectSyms.ContainsKey(ENABLE_LABEL_NEWLINE)) { settings.SetBool(AppSettings.SRCGEN_LONG_LABEL_NEW_LINE, true); } + if (project.ProjectProps.ProjectSyms.ContainsKey(ENABLE_CYCLE_COUNTS)) { + settings.SetBool(AppSettings.SRCGEN_SHOW_CYCLE_COUNTS, true); + } } private DisasmProject InstantiateProject(string dataPathName,