From 728966f8d2dcf28627b3fc41a4676d571e65019a Mon Sep 17 00:00:00 2001 From: Andy McFadden Date: Sun, 11 Oct 2020 18:38:04 -0700 Subject: [PATCH] Add W65C02S support, part 4 (of 4) Added 20233-rockwell unit test to exercise the new opcodes. Nothing too fancy. Fixed branch offset computation. (issue #87) --- SourceGen/CodeAnalysis.cs | 2 +- SourceGen/SGTestData/20233-rockwell | 1 + SourceGen/SGTestData/20233-rockwell.dis65 | 95 +++++++++++++++++++ .../Expected/20233-rockwell_64tass.S | 31 ++++++ .../Expected/20233-rockwell_Merlin32.S | 30 ++++++ .../SGTestData/Expected/20233-rockwell_acme.S | 32 +++++++ .../SGTestData/Expected/20233-rockwell_cc65.S | 32 +++++++ .../Expected/20233-rockwell_cc65.cfg | 11 +++ SourceGen/SGTestData/Source/20233-rockwell.S | 43 +++++++++ 9 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 SourceGen/SGTestData/20233-rockwell create mode 100644 SourceGen/SGTestData/20233-rockwell.dis65 create mode 100644 SourceGen/SGTestData/Expected/20233-rockwell_64tass.S create mode 100644 SourceGen/SGTestData/Expected/20233-rockwell_Merlin32.S create mode 100644 SourceGen/SGTestData/Expected/20233-rockwell_acme.S create mode 100644 SourceGen/SGTestData/Expected/20233-rockwell_cc65.S create mode 100644 SourceGen/SGTestData/Expected/20233-rockwell_cc65.cfg create mode 100644 SourceGen/SGTestData/Source/20233-rockwell.S diff --git a/SourceGen/CodeAnalysis.cs b/SourceGen/CodeAnalysis.cs index 935cb71..785f9f5 100644 --- a/SourceGen/CodeAnalysis.cs +++ b/SourceGen/CodeAnalysis.cs @@ -946,7 +946,7 @@ namespace SourceGen { // function. We totally ignore the DP byte. mAnattribs[offset].OperandAddress = Asm65.Helper.RelOffset16(mAnattribs[offset].Address, - (sbyte)(operand << 8)) | bank; + (sbyte)(operand >> 8)) | bank; break; case OpDef.AddressMode.PCRelLong: case OpDef.AddressMode.StackPCRelLong: diff --git a/SourceGen/SGTestData/20233-rockwell b/SourceGen/SGTestData/20233-rockwell new file mode 100644 index 0000000..5af3dd4 --- /dev/null +++ b/SourceGen/SGTestData/20233-rockwell @@ -0,0 +1 @@ +`Ÿ`€€€ê'·G × g0÷0/ý¿úO ÷ß ôo0ñÿ0îê` \ No newline at end of file diff --git a/SourceGen/SGTestData/20233-rockwell.dis65 b/SourceGen/SGTestData/20233-rockwell.dis65 new file mode 100644 index 0000000..3b6b1b1 --- /dev/null +++ b/SourceGen/SGTestData/20233-rockwell.dis65 @@ -0,0 +1,95 @@ +### 6502bench SourceGen dis65 v1.0 ### +{ +"_ContentVersion":4, +"FileDataLength":44, +"FileDataCrc32":-1269997697, +"ProjectProps":{ +"CpuName":"W65C02", +"IncludeUndocumentedInstr":false, +"TwoByteBrk":false, +"EntryFlags":32702671, +"AutoLabelStyle":"Simple", +"AnalysisParams":{ +"AnalyzeUncategorizedData":true, +"DefaultTextScanMode":"LowHighAscii", +"MinCharsForString":4, +"SeekNearbyTargets":true, +"UseRelocData":false, +"SmartPlpHandling":false, +"SmartPlbHandling":true}, + +"PlatformSymbolFileIdentifiers":[], +"ExtensionScriptFileIdentifiers":[], +"ProjectSyms":{ +"G_DP":{ +"DataDescriptor":{ +"Length":1, +"Format":"NumericLE", +"SubFormat":"Hex", +"SymbolRef":null}, + +"Comment":"", +"HasWidth":false, +"Direction":"ReadWrite", +"MultiMask":null, +"Label":"G_DP", +"Value":32, +"Source":"Project", +"Type":"ExternalAddr", +"LabelAnno":"None"}}}, + +"AddressMap":[{ +"Offset":0, +"Addr":4096}], +"TypeHints":[{ +"Low":0, +"High":0, +"Hint":"Code"}], +"StatusFlagOverrides":{ +}, + +"Comments":{ +}, + +"LongComments":{ +}, + +"Notes":{ +}, + +"UserLabels":{ +}, + +"OperandFormats":{ +}, + +"LvTables":{ +"11":{ +"Variables":[{ +"DataDescriptor":{ +"Length":1, +"Format":"NumericLE", +"SubFormat":"Hex", +"SymbolRef":null}, + +"Comment":"", +"HasWidth":true, +"Direction":"ReadWrite", +"MultiMask":null, +"Label":"L_DP", +"Value":48, +"Source":"Variable", +"Type":"ExternalAddr", +"LabelAnno":"None"}], +"ClearPrevious":false}}, + +"Visualizations":[], +"VisualizationAnimations":[], +"VisualizationSets":{ +}, + +"RelocList":{ +}, + +"DbrValues":{ +}} diff --git a/SourceGen/SGTestData/Expected/20233-rockwell_64tass.S b/SourceGen/SGTestData/Expected/20233-rockwell_64tass.S new file mode 100644 index 0000000..4cff80f --- /dev/null +++ b/SourceGen/SGTestData/Expected/20233-rockwell_64tass.S @@ -0,0 +1,31 @@ + .cpu "w65c02" +G_DP = $20 + +* = $1000 + bbr 0,$10,L1004 + rts + +L1004 bbs 1,$10,_L100B + rts + + .byte $80 + .byte $80 + .byte $80 + +L_DP .var $30 +_L100B nop + rmb 2,$10 + smb 3,$10 + rmb 4,G_DP + smb 5,G_DP + rmb 6,L_DP + smb 7,L_DP +_L1018 bbr 2,$10,_L1018 + bbs 3,$10,_L1018 + bbr 4,$20,_L1018 + bbs 5,$20,_L1018 + bbr 6,$30,_L1018 + bbs 7,$30,_L1018 + nop + rts + diff --git a/SourceGen/SGTestData/Expected/20233-rockwell_Merlin32.S b/SourceGen/SGTestData/Expected/20233-rockwell_Merlin32.S new file mode 100644 index 0000000..0cceea5 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20233-rockwell_Merlin32.S @@ -0,0 +1,30 @@ +G_DP equ $20 + + org $1000 + dfb $0f,$10,$01 + rts + +L1004 dfb $9f,$10,$04 + rts + + dfb $80 + dfb $80 + dfb $80 + +]L_DP equ $30 +:L100B nop + dfb $27,$10 + dfb $b7,$10 + dfb $47,$20 + dfb $d7,$20 + dfb $67,$30 + dfb $f7,$30 +:L1018 dfb $2f,$10,$fd + dfb $bf,$10,$fa + dfb $4f,$20,$f7 + dfb $df,$20,$f4 + dfb $6f,$30,$f1 + dfb $ff,$30,$ee + nop + rts + diff --git a/SourceGen/SGTestData/Expected/20233-rockwell_acme.S b/SourceGen/SGTestData/Expected/20233-rockwell_acme.S new file mode 100644 index 0000000..49c14fc --- /dev/null +++ b/SourceGen/SGTestData/Expected/20233-rockwell_acme.S @@ -0,0 +1,32 @@ + !cpu w65c02 +G_DP = $20 + +* = $1000 + bbr0 $10,L1004 + rts + +L1004 bbs1 $10,@L100B + rts + + !byte $80 + !byte $80 + !byte $80 + + !zone Z00000b +.L_DP = $30 +@L100B nop + rmb2 $10 + smb3 $10 + rmb4 G_DP + smb5 G_DP + rmb6 .L_DP + smb7 .L_DP +@L1018 bbr2 $10,@L1018 + bbs3 $10,@L1018 + bbr4 $20,@L1018 + bbs5 $20,@L1018 + bbr6 $30,@L1018 + bbs7 $30,@L1018 + nop + rts + diff --git a/SourceGen/SGTestData/Expected/20233-rockwell_cc65.S b/SourceGen/SGTestData/Expected/20233-rockwell_cc65.S new file mode 100644 index 0000000..57bf0de --- /dev/null +++ b/SourceGen/SGTestData/Expected/20233-rockwell_cc65.S @@ -0,0 +1,32 @@ + .setcpu "65C02" +G_DP = $20 + +; .segment "SEG000" + .org $1000 + bbr0 $10,L1004 + rts + +L1004: bbs1 $10,L100B + rts + + .byte $80 + .byte $80 + .byte $80 + +L_DP .set $30 +L100B: nop + rmb2 $10 + smb3 $10 + rmb4 G_DP + smb5 G_DP + rmb6 L_DP + smb7 L_DP +@L1018: bbr2 $10,@L1018 + bbs3 $10,@L1018 + bbr4 $20,@L1018 + bbs5 $20,@L1018 + bbr6 $30,@L1018 + bbs7 $30,@L1018 + nop + rts + diff --git a/SourceGen/SGTestData/Expected/20233-rockwell_cc65.cfg b/SourceGen/SGTestData/Expected/20233-rockwell_cc65.cfg new file mode 100644 index 0000000..fcafbed --- /dev/null +++ b/SourceGen/SGTestData/Expected/20233-rockwell_cc65.cfg @@ -0,0 +1,11 @@ +# 6502bench SourceGen generated linker script for 20233-rockwell +MEMORY { + MAIN: file=%O, start=%S, size=65536; +# MEM000: file=%O, start=$1000, size=44; +} +SEGMENTS { + CODE: load=MAIN, type=rw; +# SEG000: load=MEM000, type=rw; +} +FEATURES {} +SYMBOLS {} diff --git a/SourceGen/SGTestData/Source/20233-rockwell.S b/SourceGen/SGTestData/Source/20233-rockwell.S new file mode 100644 index 0000000..406733f --- /dev/null +++ b/SourceGen/SGTestData/Source/20233-rockwell.S @@ -0,0 +1,43 @@ +; Copyright 2020 faddenSoft. All Rights Reserved. +; See the LICENSE.txt file for distribution terms (Apache 2.0). +; +; Test Rockwell's 65C02 extensions. +; Assembler: ACME + + !cpu w65c02 +* = $1000 + +U_DP = $10 ;don't define +G_DP = $20 ;define as global project symbol +L_DP = $30 ;define as local variable + +; Verify both halves of branches are traced. In theory, BBR followed +; by BBS on the same bit number should be always-taken, but we don't +; try to model memory. + + bbr0 U_DP,cont0 + rts +cont0 bbs1 U_DP,cont1 + rts + !byte $80,$80,$80 ;filler to get different branch offset +cont1 nop + +; Access the three zero-page values in different ways. Also exercise +; backward and to-self branches. +; EDIT: add $30 to a local variable table here + rmb2 U_DP + smb3 U_DP + rmb4 G_DP + smb5 G_DP + rmb6 L_DP + smb7 L_DP + +bback bbr2 U_DP,bback + bbs3 U_DP,bback + bbr4 G_DP,bback + bbs5 G_DP,bback + bbr6 L_DP,bback + bbs7 L_DP,bback + + nop + rts