diff --git a/SourceGen/SGTestData/20100-label-dp b/SourceGen/SGTestData/20100-label-dp new file mode 100644 index 0000000..09152ee Binary files /dev/null and b/SourceGen/SGTestData/20100-label-dp differ diff --git a/SourceGen/SGTestData/20100-label-dp.dis65 b/SourceGen/SGTestData/20100-label-dp.dis65 new file mode 100644 index 0000000..4ed928e --- /dev/null +++ b/SourceGen/SGTestData/20100-label-dp.dis65 @@ -0,0 +1,72 @@ +### 6502bench SourceGen dis65 v1.0 ### +{ +"_ContentVersion":4, +"FileDataLength":607, +"FileDataCrc32":472348517, +"ProjectProps":{ +"CpuName":"6502", +"IncludeUndocumentedInstr":true, +"TwoByteBrk":false, +"EntryFlags":32702671, +"AutoLabelStyle":"Simple", +"AnalysisParams":{ +"AnalyzeUncategorizedData":true, +"DefaultTextScanMode":"LowHighAscii", +"MinCharsForString":4, +"SeekNearbyTargets":true, +"UseRelocData":false, +"SmartPlpHandling":false, +"SmartPlbHandling":true}, + +"PlatformSymbolFileIdentifiers":[], +"ExtensionScriptFileIdentifiers":[], +"ProjectSyms":{ +}}, + +"AddressMap":[{ +"Offset":0, +"Addr":4096}, + +{ +"Offset":598, +"Addr":128}], +"TypeHints":[{ +"Low":0, +"High":0, +"Hint":"Code"}, + +{ +"Low":598, +"High":598, +"Hint":"Code"}], +"StatusFlagOverrides":{ +}, + +"Comments":{ +}, + +"LongComments":{ +}, + +"Notes":{ +}, + +"UserLabels":{ +}, + +"OperandFormats":{ +}, + +"LvTables":{ +}, + +"Visualizations":[], +"VisualizationAnimations":[], +"VisualizationSets":{ +}, + +"RelocList":{ +}, + +"DbrValues":{ +}} diff --git a/SourceGen/SGTestData/Expected/20100-label-dp_64tass.S b/SourceGen/SGTestData/Expected/20100-label-dp_64tass.S new file mode 100644 index 0000000..ae18b78 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20100-label-dp_64tass.S @@ -0,0 +1,302 @@ + .cpu "6502i" +* = $1000 + jsr L1035 + jsr L1038 + jsr L1059 + jsr L107D + jsr L109E + jsr L10BD + jsr L10C0 + jsr L10E1 + jsr L1100 + jsr L1103 + jsr L1116 + jsr L1124 + jsr L1169 + jsr L11AE + jsr L11F3 + jsr L1238 + nop + nop + nop + brk + + .byte $80 + +L1035 ora (L0080,x) + jam + +L1038 slo (L0080,x) + .byte $04,$80 + ora L0080 + asl L0080 + slo L0080 + php + ora #$80 + asl a + anc #$80 + .byte $0c,$86,$00 + ora @wL0086 + asl @wL0086 + slo @wL0086 + bpl _L1056 +_L1056 ora (L0080),y + .byte $12 + +L1059 slo (L0080),y + .byte $14,$80 + ora L0080,x + asl L0080,x + slo L0080,x + clc + ora L0086,y + .byte $1a + slo L0086,y + .byte $1c,$86,$00 + ora @wL0086,x + asl @wL0086,x + slo @wL0086,x + jsr L0086 + and (L0080,x) + .byte $22 + +L107D rla (L0080,x) + bit L0080 + and L0080 + rol L0080 + rla L0080 + plp + and #$80 + rol a + .byte $2b,$80 + bit @wL0086 + and @wL0086 + rol @wL0086 + rla @wL0086 + bmi _L109B +_L109B and (L0080),y + .byte $32 + +L109E rla (L0080),y + .byte $34,$80 + and L0080,x + rol L0080,x + rla L0080,x + sec + and L0086,y + .byte $3a + rla L0086,y + .byte $3c,$86,$00 + and @wL0086,x + rol @wL0086,x + rla @wL0086,x + rti + +L10BD eor (L0080,x) + .byte $42 + +L10C0 sre (L0080,x) + .byte $44,$80 + eor L0080 + lsr L0080 + sre L0080 + pha + eor #$80 + lsr a + alr #$80 + jmp _L10D3 + +_L10D3 eor @wL0086 + lsr @wL0086 + sre @wL0086 + bvc _L10DE +_L10DE eor (L0080),y + .byte $52 + +L10E1 sre (L0080),y + .byte $54,$80 + eor L0080,x + lsr L0080,x + sre L0080,x + cli + eor L0086,y + .byte $5a + sre L0086,y + .byte $5c,$86,$00 + eor @wL0086,x + lsr @wL0086,x + sre @wL0086,x + rts + +L1100 adc (L0080,x) + .byte $62 + +L1103 rra (L0080,x) + .byte $64,$80 + adc L0080 + ror L0080 + rra L0080 + pla + adc #$80 + ror a + arr #$80 + jmp (L0086) + +L1116 adc @wL0086 + ror @wL0086 + rra @wL0086 + bvs _L1121 +_L1121 adc (L0080),y + .byte $72 + +L1124 rra (L0080),y + .byte $74,$80 + adc L0080,x + ror L0080,x + rra L0080,x + sei + adc L0086,y + .byte $7a + rra L0086,y + .byte $7c,$86,$00 + adc @wL0086,x + ror @wL0086,x + rra @wL0086,x + .byte $80,$80 + sta (L0080,x) + .byte $82,$80 + sax (L0080,x) + sty L0080 + sta L0080 + stx L0080 + sax L0080 + dey + .byte $89,$80 + txa + ane #$80 + sty @wL0086 + sta @wL0086 + stx @wL0086 + sax @wL0086 + bcc _L1166 +_L1166 sta (L0080),y + .byte $92 + +L1169 .byte $93,$80 + sty L0080,x + sta L0080,x + stx L0080,y + sax L0080,y + tya + sta L0086,y + txs + tas L0086,y + shy @wL0086,x + sta @wL0086,x + shx L0086,y + sha L0086,y + ldy #$80 + lda (L0080,x) + ldx #$80 + lax (L0080,x) + ldy L0080 + lda L0080 + ldx L0080 + lax L0080 + tay + lda #$80 + tax + lax #$80 + ldy @wL0086 + lda @wL0086 + ldx @wL0086 + lax @wL0086 + bcs _L11AB +_L11AB lda (L0080),y + .byte $b2 + +L11AE lax (L0080),y + ldy L0080,x + lda L0080,x + ldx L0080,y + lax L0080,y + clv + lda L0086,y + tsx + las L0086,y + ldy @wL0086,x + lda @wL0086,x + ldx @wL0086,y + lax @wL0086,y + cpy #$80 + cmp (L0080,x) + .byte $c2,$80 + dcp (L0080,x) + cpy L0080 + cmp L0080 + dec L0080 + dcp L0080 + iny + cmp #$80 + dex + sbx #$80 + cpy @wL0086 + cmp @wL0086 + dec @wL0086 + dcp @wL0086 + bne _L11F0 +_L11F0 cmp (L0080),y + .byte $d2 + +L11F3 dcp (L0080),y + .byte $d4,$80 + cmp L0080,x + dec L0080,x + dcp L0080,x + cld + cmp L0086,y + .byte $da + dcp L0086,y + .byte $dc,$86,$00 + cmp @wL0086,x + dec @wL0086,x + dcp @wL0086,x + cpx #$80 + sbc (L0080,x) + .byte $e2,$80 + isc (L0080,x) + cpx L0080 + sbc L0080 + inc L0080 + isc L0080 + inx + sbc #$80 + nop + .byte $eb,$80 + cpx @wL0086 + sbc @wL0086 + inc @wL0086 + isc @wL0086 + beq _L1235 +_L1235 sbc (L0080),y + .byte $f2 + +L1238 isc (L0080),y + .byte $f4,$80 + sbc L0080,x + inc L0080,x + isc L0080,x + sed + sbc L0086,y + .byte $fa + isc L0086,y + .byte $fc,$86,$00 + sbc @wL0086,x + inc @wL0086,x + isc @wL0086,x + .logical $0080 +L0080 bit _L0082 +_L0082 bit _L0082 + bit _L0082 +L0086 bit @wL0086 + .here diff --git a/SourceGen/SGTestData/Expected/20100-label-dp_acme.S b/SourceGen/SGTestData/Expected/20100-label-dp_acme.S new file mode 100644 index 0000000..4565e15 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20100-label-dp_acme.S @@ -0,0 +1,304 @@ + !cpu 6510 +* = $0000 + !pseudopc $1000 { + jsr L1035 + jsr L1038 + jsr L1059 + jsr L107D + jsr L109E + jsr L10BD + jsr L10C0 + jsr L10E1 + jsr L1100 + jsr L1103 + jsr L1116 + jsr L1124 + jsr L1169 + jsr L11AE + jsr L11F3 + jsr L1238 + nop + nop + nop + brk + + !byte $80 + +L1035 ora (L0080,x) + jam + +L1038 slo (L0080,x) + !byte $04,$80 + ora+1 L0080 + asl+1 L0080 + slo+1 L0080 + php + ora #$80 + asl + anc #$80 + !byte $0c,$86,$00 + ora+2 L0086 + asl+2 L0086 + slo+2 L0086 + bpl @L1056 +@L1056 ora (L0080),y + !byte $12 + +L1059 slo (L0080),y + !byte $14,$80 + ora+1 L0080,x + asl+1 L0080,x + slo+1 L0080,x + clc + ora L0086,y + !byte $1a + slo L0086,y + !byte $1c,$86,$00 + ora+2 L0086,x + asl+2 L0086,x + slo+2 L0086,x + jsr L0086 + and (L0080,x) + !byte $22 + +L107D rla (L0080,x) + bit+1 L0080 + and+1 L0080 + rol+1 L0080 + rla+1 L0080 + plp + and #$80 + rol + !byte $2b,$80 + bit+2 L0086 + and+2 L0086 + rol+2 L0086 + rla+2 L0086 + bmi @L109B +@L109B and (L0080),y + !byte $32 + +L109E rla (L0080),y + !byte $34,$80 + and+1 L0080,x + rol+1 L0080,x + rla+1 L0080,x + sec + and L0086,y + !byte $3a + rla L0086,y + !byte $3c,$86,$00 + and+2 L0086,x + rol+2 L0086,x + rla+2 L0086,x + rti + +L10BD eor (L0080,x) + !byte $42 + +L10C0 sre (L0080,x) + !byte $44,$80 + eor+1 L0080 + lsr+1 L0080 + sre+1 L0080 + pha + eor #$80 + lsr + asr #$80 + jmp @L10D3 + +@L10D3 eor+2 L0086 + lsr+2 L0086 + sre+2 L0086 + bvc @L10DE +@L10DE eor (L0080),y + !byte $52 + +L10E1 sre (L0080),y + !byte $54,$80 + eor+1 L0080,x + lsr+1 L0080,x + sre+1 L0080,x + cli + eor L0086,y + !byte $5a + sre L0086,y + !byte $5c,$86,$00 + eor+2 L0086,x + lsr+2 L0086,x + sre+2 L0086,x + rts + +L1100 adc (L0080,x) + !byte $62 + +L1103 rra (L0080,x) + !byte $64,$80 + adc+1 L0080 + ror+1 L0080 + rra+1 L0080 + pla + adc #$80 + ror + arr #$80 + jmp (L0086) + +L1116 adc+2 L0086 + ror+2 L0086 + rra+2 L0086 + bvs @L1121 +@L1121 adc (L0080),y + !byte $72 + +L1124 rra (L0080),y + !byte $74,$80 + adc+1 L0080,x + ror+1 L0080,x + rra+1 L0080,x + sei + adc L0086,y + !byte $7a + rra L0086,y + !byte $7c,$86,$00 + adc+2 L0086,x + ror+2 L0086,x + rra+2 L0086,x + !byte $80,$80 + sta (L0080,x) + !byte $82,$80 + sax (L0080,x) + sty+1 L0080 + sta+1 L0080 + stx+1 L0080 + sax+1 L0080 + dey + !byte $89,$80 + txa + ane #$80 + sty+2 L0086 + sta+2 L0086 + stx+2 L0086 + sax+2 L0086 + bcc @L1166 +@L1166 sta (L0080),y + !byte $92 + +L1169 sha (L0080),y + sty+1 L0080,x + sta+1 L0080,x + stx+1 L0080,y + sax+1 L0080,y + tya + sta L0086,y + txs + tas L0086,y + shy+2 L0086,x + sta+2 L0086,x + shx L0086,y + sha L0086,y + ldy #$80 + lda (L0080,x) + ldx #$80 + lax (L0080,x) + ldy+1 L0080 + lda+1 L0080 + ldx+1 L0080 + lax+1 L0080 + tay + lda #$80 + tax + !byte $ab,$80 + ldy+2 L0086 + lda+2 L0086 + ldx+2 L0086 + lax+2 L0086 + bcs @L11AB +@L11AB lda (L0080),y + !byte $b2 + +L11AE lax (L0080),y + ldy+1 L0080,x + lda+1 L0080,x + ldx+1 L0080,y + lax+1 L0080,y + clv + lda L0086,y + tsx + las L0086,y + ldy+2 L0086,x + lda+2 L0086,x + ldx+2 L0086,y + lax+2 L0086,y + cpy #$80 + cmp (L0080,x) + !byte $c2,$80 + dcp (L0080,x) + cpy+1 L0080 + cmp+1 L0080 + dec+1 L0080 + dcp+1 L0080 + iny + cmp #$80 + dex + sbx #$80 + cpy+2 L0086 + cmp+2 L0086 + dec+2 L0086 + dcp+2 L0086 + bne @L11F0 +@L11F0 cmp (L0080),y + !byte $d2 + +L11F3 dcp (L0080),y + !byte $d4,$80 + cmp+1 L0080,x + dec+1 L0080,x + dcp+1 L0080,x + cld + cmp L0086,y + !byte $da + dcp L0086,y + !byte $dc,$86,$00 + cmp+2 L0086,x + dec+2 L0086,x + dcp+2 L0086,x + cpx #$80 + sbc (L0080,x) + !byte $e2,$80 + isc (L0080,x) + cpx+1 L0080 + sbc+1 L0080 + inc+1 L0080 + isc+1 L0080 + inx + sbc #$80 + nop + !byte $eb,$80 + cpx+2 L0086 + sbc+2 L0086 + inc+2 L0086 + isc+2 L0086 + beq @L1235 +@L1235 sbc (L0080),y + !byte $f2 + +L1238 isc (L0080),y + !byte $f4,$80 + sbc+1 L0080,x + inc+1 L0080,x + isc+1 L0080,x + sed + sbc L0086,y + !byte $fa + isc L0086,y + !byte $fc,$86,$00 + sbc+2 L0086,x + inc+2 L0086,x + isc+2 L0086,x + } ;!pseudopc + !pseudopc $0080 { +L0080 bit+1 @L0082 +@L0082 bit+1 @L0082 + bit+1 @L0082 +L0086 bit+2 L0086 + } ;!pseudopc diff --git a/SourceGen/SGTestData/Expected/20100-label-dp_cc65.S b/SourceGen/SGTestData/Expected/20100-label-dp_cc65.S new file mode 100644 index 0000000..ae50bb5 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20100-label-dp_cc65.S @@ -0,0 +1,303 @@ + .setcpu "6502X" +; .segment "SEG000" + .org $1000 + jsr L1035 + jsr L1038 + jsr L1059 + jsr L107D + jsr L109E + jsr L10BD + jsr L10C0 + jsr L10E1 + jsr L1100 + jsr L1103 + jsr L1116 + jsr L1124 + jsr L1169 + jsr L11AE + jsr L11F3 + jsr L1238 + nop + nop + nop + brk + + .byte $80 + +L1035: ora (L0080,x) + jam + +L1038: slo (L0080,x) + .byte $04,$80 + ora z:L0080 + asl z:L0080 + slo z:L0080 + php + ora #$80 + asl A + anc #$80 + .byte $0c,$86,$00 + ora a:L0086 + asl a:L0086 + slo a:L0086 + bpl @L1056 +@L1056: ora (L0080),y + .byte $12 + +L1059: slo (L0080),y + .byte $14,$80 + ora z:L0080,x + asl z:L0080,x + slo z:L0080,x + clc + ora L0086,y + .byte $1a + slo L0086,y + .byte $1c,$86,$00 + ora a:L0086,x + asl a:L0086,x + slo a:L0086,x + jsr L0086 + and (L0080,x) + .byte $22 + +L107D: rla (L0080,x) + bit z:L0080 + and z:L0080 + rol z:L0080 + rla z:L0080 + plp + and #$80 + rol A + .byte $2b,$80 + bit a:L0086 + and a:L0086 + rol a:L0086 + rla a:L0086 + bmi @L109B +@L109B: and (L0080),y + .byte $32 + +L109E: rla (L0080),y + .byte $34,$80 + and z:L0080,x + rol z:L0080,x + rla z:L0080,x + sec + and L0086,y + .byte $3a + rla L0086,y + .byte $3c,$86,$00 + and a:L0086,x + rol a:L0086,x + rla a:L0086,x + rti + +L10BD: eor (L0080,x) + .byte $42 + +L10C0: sre (L0080,x) + .byte $44,$80 + eor z:L0080 + lsr z:L0080 + sre z:L0080 + pha + eor #$80 + lsr A + alr #$80 + jmp @L10D3 + +@L10D3: eor a:L0086 + lsr a:L0086 + sre a:L0086 + bvc @L10DE +@L10DE: eor (L0080),y + .byte $52 + +L10E1: sre (L0080),y + .byte $54,$80 + eor z:L0080,x + lsr z:L0080,x + sre z:L0080,x + cli + eor L0086,y + .byte $5a + sre L0086,y + .byte $5c,$86,$00 + eor a:L0086,x + lsr a:L0086,x + sre a:L0086,x + rts + +L1100: adc (L0080,x) + .byte $62 + +L1103: rra (L0080,x) + .byte $64,$80 + adc z:L0080 + ror z:L0080 + rra z:L0080 + pla + adc #$80 + ror A + arr #$80 + jmp (L0086) + +L1116: adc a:L0086 + ror a:L0086 + rra a:L0086 + bvs @L1121 +@L1121: adc (L0080),y + .byte $72 + +L1124: rra (L0080),y + .byte $74,$80 + adc z:L0080,x + ror z:L0080,x + rra z:L0080,x + sei + adc L0086,y + .byte $7a + rra L0086,y + .byte $7c,$86,$00 + adc a:L0086,x + ror a:L0086,x + rra a:L0086,x + .byte $80,$80 + sta (L0080,x) + .byte $82,$80 + sax (L0080,x) + sty z:L0080 + sta z:L0080 + stx z:L0080 + sax z:L0080 + dey + .byte $89,$80 + txa + ane #$80 + sty a:L0086 + sta a:L0086 + stx a:L0086 + sax a:L0086 + bcc @L1166 +@L1166: sta (L0080),y + .byte $92 + +L1169: sha (L0080),y + sty z:L0080,x + sta z:L0080,x + stx z:L0080,y + sax z:L0080,y + tya + sta L0086,y + txs + tas L0086,y + shy a:L0086,x + sta a:L0086,x + shx L0086,y + sha L0086,y + ldy #$80 + lda (L0080,x) + ldx #$80 + lax (L0080,x) + ldy z:L0080 + lda z:L0080 + ldx z:L0080 + lax z:L0080 + tay + lda #$80 + tax + lax #$80 + ldy a:L0086 + lda a:L0086 + ldx a:L0086 + lax a:L0086 + bcs @L11AB +@L11AB: lda (L0080),y + .byte $b2 + +L11AE: lax (L0080),y + ldy z:L0080,x + lda z:L0080,x + ldx z:L0080,y + lax z:L0080,y + clv + lda L0086,y + tsx + las L0086,y + ldy a:L0086,x + lda a:L0086,x + ldx a:L0086,y + lax a:L0086,y + cpy #$80 + cmp (L0080,x) + .byte $c2,$80 + dcp (L0080,x) + cpy z:L0080 + cmp z:L0080 + dec z:L0080 + dcp z:L0080 + iny + cmp #$80 + dex + axs #$80 + cpy a:L0086 + cmp a:L0086 + dec a:L0086 + dcp a:L0086 + bne @L11F0 +@L11F0: cmp (L0080),y + .byte $d2 + +L11F3: dcp (L0080),y + .byte $d4,$80 + cmp z:L0080,x + dec z:L0080,x + dcp z:L0080,x + cld + cmp L0086,y + .byte $da + dcp L0086,y + .byte $dc,$86,$00 + cmp a:L0086,x + dec a:L0086,x + dcp a:L0086,x + cpx #$80 + sbc (L0080,x) + .byte $e2,$80 + isc (L0080,x) + cpx z:L0080 + sbc z:L0080 + inc z:L0080 + isc z:L0080 + inx + sbc #$80 + nop + .byte $eb,$80 + cpx a:L0086 + sbc a:L0086 + inc a:L0086 + isc a:L0086 + beq @L1235 +@L1235: sbc (L0080),y + .byte $f2 + +L1238: isc (L0080),y + .byte $f4,$80 + sbc z:L0080,x + inc z:L0080,x + isc z:L0080,x + sed + sbc L0086,y + .byte $fa + isc L0086,y + .byte $fc,$86,$00 + sbc a:L0086,x + inc a:L0086,x + isc a:L0086,x +; .segment "SEG001" + .org $0080 +L0080: bit z:@L0082 +@L0082: bit @L0082 + bit @L0082 +L0086: bit a:L0086 diff --git a/SourceGen/SGTestData/Expected/20100-label-dp_cc65.cfg b/SourceGen/SGTestData/Expected/20100-label-dp_cc65.cfg new file mode 100644 index 0000000..7b1b152 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20100-label-dp_cc65.cfg @@ -0,0 +1,13 @@ +# 6502bench SourceGen generated linker script for 20100-label-dp +MEMORY { + MAIN: file=%O, start=%S, size=65536; +# MEM000: file=%O, start=$1000, size=598; +# MEM001: file=%O, start=$0080, size=9; +} +SEGMENTS { + CODE: load=MAIN, type=rw; +# SEG000: load=MEM000, type=rw; +# SEG001: load=MEM001, type=rw; +} +FEATURES {} +SYMBOLS {} diff --git a/SourceGen/SGTestData/Expected/20100-label-dp_merlin32.S b/SourceGen/SGTestData/Expected/20100-label-dp_merlin32.S new file mode 100644 index 0000000..8b67f68 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20100-label-dp_merlin32.S @@ -0,0 +1,300 @@ + org $1000 + jsr L1035 + jsr L1038 + jsr L1059 + jsr L107D + jsr L109E + jsr L10BD + jsr L10C0 + jsr L10E1 + jsr L1100 + jsr L1103 + jsr L1116 + jsr L1124 + jsr L1169 + jsr L11AE + jsr L11F3 + jsr L1238 + nop + nop + nop + brk + + dfb $80 + +L1035 dfb $01,$80 + dfb $02 + +L1038 dfb $03,$80 + dfb $04,$80 + ora L0080 + asl L0080 + dfb $07,$80 + php + ora #$80 + asl A + dfb $0b,$80 + dfb $0c,$86,$00 + ora: L0086 + asl: L0086 + dfb $0f,$86,$00 + bpl :L1056 +:L1056 ora (L0080),y + dfb $12 + +L1059 dfb $13,$80 + dfb $14,$80 + ora L0080,x + asl L0080,x + dfb $17,$80 + clc + ora L0086,y + dfb $1a + dfb $1b,$86,$00 + dfb $1c,$86,$00 + ora: L0086,x + asl: L0086,x + dfb $1f,$86,$00 + jsr L0086 + dfb $21,$80 + dfb $22 + +L107D dfb $23,$80 + bit L0080 + and L0080 + rol L0080 + dfb $27,$80 + plp + and #$80 + rol A + dfb $2b,$80 + bit: L0086 + and: L0086 + rol: L0086 + dfb $2f,$86,$00 + bmi :L109B +:L109B and (L0080),y + dfb $32 + +L109E dfb $33,$80 + dfb $34,$80 + and L0080,x + rol L0080,x + dfb $37,$80 + sec + and L0086,y + dfb $3a + dfb $3b,$86,$00 + dfb $3c,$86,$00 + and: L0086,x + rol: L0086,x + dfb $3f,$86,$00 + rti + +L10BD dfb $41,$80 + dfb $42 + +L10C0 dfb $43,$80 + dfb $44,$80 + eor L0080 + lsr L0080 + dfb $47,$80 + pha + eor #$80 + lsr A + dfb $4b,$80 + jmp :L10D3 + +:L10D3 eor: L0086 + lsr: L0086 + dfb $4f,$86,$00 + bvc :L10DE +:L10DE eor (L0080),y + dfb $52 + +L10E1 dfb $53,$80 + dfb $54,$80 + eor L0080,x + lsr L0080,x + dfb $57,$80 + cli + eor L0086,y + dfb $5a + dfb $5b,$86,$00 + dfb $5c,$86,$00 + eor: L0086,x + lsr: L0086,x + dfb $5f,$86,$00 + rts + +L1100 dfb $61,$80 + dfb $62 + +L1103 dfb $63,$80 + dfb $64,$80 + adc L0080 + ror L0080 + dfb $67,$80 + pla + adc #$80 + ror A + dfb $6b,$80 + jmp (L0086) + +L1116 adc: L0086 + ror: L0086 + dfb $6f,$86,$00 + bvs :L1121 +:L1121 adc (L0080),y + dfb $72 + +L1124 dfb $73,$80 + dfb $74,$80 + adc L0080,x + ror L0080,x + dfb $77,$80 + sei + adc L0086,y + dfb $7a + dfb $7b,$86,$00 + dfb $7c,$86,$00 + adc: L0086,x + ror: L0086,x + dfb $7f,$86,$00 + dfb $80,$80 + dfb $81,$80 + dfb $82,$80 + dfb $83,$80 + sty L0080 + sta L0080 + stx L0080 + dfb $87,$80 + dey + dfb $89,$80 + txa + dfb $8b,$80 + sty: L0086 + sta: L0086 + stx: L0086 + dfb $8f,$86,$00 + bcc :L1166 +:L1166 sta (L0080),y + dfb $92 + +L1169 dfb $93,$80 + dfb $94,$80 + sta L0080,x + dfb $96,$80 + dfb $97,$80 + tya + sta L0086,y + txs + dfb $9b,$86,$00 + dfb $9c,$86,$00 + sta: L0086,x + dfb $9e,$86,$00 + dfb $9f,$86,$00 + ldy #$80 + dfb $a1,$80 + ldx #$80 + dfb $a3,$80 + ldy L0080 + lda L0080 + ldx L0080 + dfb $a7,$80 + tay + lda #$80 + tax + dfb $ab,$80 + ldy: L0086 + lda: L0086 + ldx: L0086 + dfb $af,$86,$00 + bcs :L11AB +:L11AB lda (L0080),y + dfb $b2 + +L11AE dfb $b3,$80 + ldy L0080,x + lda L0080,x + ldx L0080,y + dfb $b7,$80 + clv + lda L0086,y + tsx + dfb $bb,$86,$00 + ldy: L0086,x + lda: L0086,x + ldx: L0086,y + dfb $bf,$86,$00 + cpy #$80 + dfb $c1,$80 + dfb $c2,$80 + dfb $c3,$80 + cpy L0080 + cmp L0080 + dec L0080 + dfb $c7,$80 + iny + cmp #$80 + dex + dfb $cb,$80 + cpy: L0086 + cmp: L0086 + dec: L0086 + dfb $cf,$86,$00 + bne :L11F0 +:L11F0 cmp (L0080),y + dfb $d2 + +L11F3 dfb $d3,$80 + dfb $d4,$80 + cmp L0080,x + dec L0080,x + dfb $d7,$80 + cld + cmp L0086,y + dfb $da + dfb $db,$86,$00 + dfb $dc,$86,$00 + cmp: L0086,x + dec: L0086,x + dfb $df,$86,$00 + cpx #$80 + dfb $e1,$80 + dfb $e2,$80 + dfb $e3,$80 + cpx L0080 + sbc L0080 + inc L0080 + dfb $e7,$80 + inx + sbc #$80 + nop + dfb $eb,$80 + cpx: L0086 + sbc: L0086 + inc: L0086 + dfb $ef,$86,$00 + beq :L1235 +:L1235 sbc (L0080),y + dfb $f2 + +L1238 dfb $f3,$80 + dfb $f4,$80 + sbc L0080,x + inc L0080,x + dfb $f7,$80 + sed + sbc L0086,y + dfb $fa + dfb $fb,$86,$00 + dfb $fc,$86,$00 + sbc: L0086,x + inc: L0086,x + dfb $ff,$86,$00 + org $0080 +L0080 bit :L0082 +:L0082 bit :L0082 + bit :L0082 +L0086 bit: L0086 diff --git a/SourceGen/SGTestData/Source/20100-label-dp.S b/SourceGen/SGTestData/Source/20100-label-dp.S new file mode 100644 index 0000000..f5edc08 --- /dev/null +++ b/SourceGen/SGTestData/Source/20100-label-dp.S @@ -0,0 +1,15 @@ +; Copyright 2018 faddenSoft. All Rights Reserved. +; See the LICENSE.txt file for distribution terms (Apache 2.0). +; +; Assembler: Merlin 32 + +ZP equ $80 ;must NOT be "$0080" + + PUT allops-common-6502.S + + org $0080 + bit _ZP +_ZP bit _ZP + bit _ZP +ABS bit: ABS +