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Update relocation data handling

Browse Source 
When we have relocation data available, the code currently skips the
process of matching an address with a label for a PEA instruction when
the instruction in question doesn't have reloc data.  This does a
great job of separating code that pushes parts of addresses from code
that pushes constants.

This change expands the behavior to exclude instructions with 16-bit
address operands that use the Data Bank Register, e.g. "LDA abs"
and "LDA abs,X".  This is particularly useful for code that accesses
structured data using the operand as the structure offset, e.g.
"LDX addr" / "LDA $0000,X"

The 20212-reloc-data test has been updated to check the behavior.
This commit is contained in:
Andy McFadden 2020-07-10 17:24:11 -07:00
parent da38bc0db8
commit cc6ebaffc5
12 changed files with 211 additions and 127 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
SourceGen/CodeAnalysis.cs
View File

@ -1221,6 +1221,8 @@ namespace SourceGen {
}
}
#region Data Bank Register management
/// <summary>
/// Data Bank Register value.
/// </summary>
@ -1410,5 +1412,6 @@ namespace SourceGen {
}
}
}
#endregion Data Bank Register management
}
}

22
SourceGen/DataAnalysis.cs
View File

@ -195,11 +195,25 @@ namespace SourceGen {
// No reloc for this instruction. If it's a relative branch we need
// to do the usual stuff, but if it's a PEA we want to treat it like
// an immediate value. The safest thing to do is blacklist PEA and
// let everything else proceed like it does without reloc data enabled.
// an immediate value. It should also be safe and useful to halt
// processing for "LDA abs" and the like.
OpDef op = mProject.CpuDef.GetOpDef(mProject.FileData[offset]);
if (op == OpDef.OpPEA_StackAbs) {
//Debug.WriteLine("NoPEA +" + offset.ToString("x6"));
bool stopHere = false;
switch (op.AddrMode) {
case OpDef.AddressMode.StackAbs: // PEA
case OpDef.AddressMode.Abs: // technically just non-PBR
case OpDef.AddressMode.AbsIndexX:
case OpDef.AddressMode.AbsIndexY:
stopHere = true;
break;
// AbsIndexXInd, AbsInd, AbsIndLong look like absolute addresses
// but use the program bank or bank 0. They're unambiguous even
// without reloc data, so no need to block them. That also goes
// for long addressing: ideally they'd have reloc data, but even if
// they don't, we might as well hook up a symbol because they can't
// mean anything else. (I think.)
}
if (stopHere) {
continue;
}
}

42
SourceGen/RuntimeData/Help/advanced.html
View File

@ -303,6 +303,9 @@ it is with the <code>JMP $1000</code> at the start of the file.</p>
<h2><a name="reloc-data">OMF Relocation Dictionaries</a></h2>
<p><i>This feature is considered experimental. Some features,
like cross-reference tracking, may not work correctly with it.</i></p>
<p>65816 code can be tricky to disassemble for a number of reasons.
24-bit addresses are formed from 16-bit data-access operands by combining
with the Data Bank Register, which often requires a bit of manual
@ -347,9 +350,42 @@ even without setting the DBR.</p>
02/318f: a9 03 00 lda #L30000 >> 16
02/3192: 8d 7a 3f sta L23F78 & $ffff +2
</pre>
<p>This feature is still considered "experimental". There are some
issues with it, e.g. the cross-reference table may show an incorrect
offset.</p>
<p>The absence of relocation data can be a useful signal as well. For
example, when pushing arguments for a toolbox call, the disassembler
can tell the difference between addresses and constants without needing
emulation or pattern-matching, because only the addresses get
relocated. Consider this bit of source code:</p>
<pre>
lda &lt;total_records
pha
pea linebuf|-16
pea linebuf+65
pea $0005
pea $0000
_Int2Dec
</pre>
<p>Without relocation data, it becomes:</p>
<pre>
02/0aa8: a5 42 lda $42
02/0aaa: 48 pha
02/0aab: f4 02 00 pea L20002 & $ffff
02/0aae: f4 03 31 pea L23103 & $ffff
02/0ab1: f4 05 00 pea L20005 & $ffff
02/0ab4: f4 00 00 pea L20000 & $ffff
02/0ab7: a2 0b 26 ldx #Int2Dec
02/0aba: 22 00 00 e1 jsl Toolbox
</pre>
<p>If we treat the non-relocated operands as constants:</p>
<pre>
02/0aa8: a5 42 lda $42
02/0aaa: 48 pha
02/0aab: f4 02 00 pea L230C2 >> 16
02/0aae: f4 03 31 pea L23103 & $ffff
02/0ab1: f4 05 00 pea $0005
02/0ab4: f4 00 00 pea $0000
02/0ab7: a2 0b 26 ldx #Int2Dec
02/0aba: 22 00 00 e1 jsl Toolbox
</pre>
<h2><a name="debug">Debug Menu Options</a></h2>

BIN
SourceGen/SGTestData/20212-reloc-data
View File

Binary file not shown.

105
SourceGen/SGTestData/20212-reloc-data.dis65
View File

@ -1,8 +1,8 @@
### 6502bench SourceGen dis65 v1.0 ###
{
"_ContentVersion":4,
"FileDataLength":282,
"FileDataCrc32":-560719478,
"FileDataLength":297,
"FileDataCrc32":-2122893303,
"ProjectProps":{
"CpuName":"65816",
"IncludeUndocumentedInstr":false,
@ -31,23 +31,23 @@
"Addr":196608},
{
"Offset":137,
"Offset":143,
"Addr":327648},
{
"Offset":169,
"Offset":175,
"Addr":327680},
{
"Offset":189,
"Offset":195,
"Addr":144470},
{
"Offset":215,
"Offset":230,
"Addr":524288},
{
"Offset":269,
"Offset":284,
"Addr":393216}],
"TypeHints":[{
"Low":0,
@ -66,25 +66,25 @@
"MaxWidth":80,
"BackgroundColor":0},
"137":{
"143":{
"Text":"Segment 03: Kind=Data; Attrs=BankRel, Dynamic; Name=\u0027PosFFE0 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"189":{
"195":{
"Text":"Segment 04: Kind=Code; Attrs=NoSpecial; Name=\u0027Bank2 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"215":{
"230":{
"Text":"Segment 05: Kind=Code; Attrs=AbsBank, Dynamic; Name=\u0027Bank8 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"269":{
"284":{
"Text":"Segment 06: Kind=Data; Attrs=0; Name=\u0027Filler \u0027",
"BoxMode":false,
"MaxWidth":80,
@ -97,25 +97,25 @@
"MaxWidth":80,
"BackgroundColor":0},
"137":{
"143":{
"Text":"Seg03: 04/ffe0 \u0027PosFFE0 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"189":{
"195":{
"Text":"Seg04: 02/3456 \u0027Bank2 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"215":{
"230":{
"Text":"Seg05: 08/0000 \u0027Bank8 \u0027",
"BoxMode":false,
"MaxWidth":80,
"BackgroundColor":0},
"269":{
"284":{
"Text":"Seg06: 06/0000 \u0027Filler \u0027",
"BoxMode":false,
"MaxWidth":80,
@ -136,60 +136,60 @@
},
"RelocList":{
"82":{
"88":{
"Width":2,
"Shift":0,
"Value":196677},
"Value":196683},
"91":{
"97":{
"Width":2,
"Shift":0,
"Value":196695},
"Value":196701},
"94":{
"100":{
"Width":2,
"Shift":0,
"Value":200773},
"Value":200779},
"98":{
"104":{
"Width":2,
"Shift":0,
"Value":196717},
"Value":196723},
"118":{
"124":{
"Width":2,
"Shift":0,
"Value":196738},
"Value":196744},
"122":{
"128":{
"Width":2,
"Shift":0,
"Value":196736},
"Value":196742},
"5":{
"Width":3,
"Shift":0,
"Value":196608},
"128":{
"134":{
"Width":3,
"Shift":0,
"Value":196677},
"Value":196683},
"132":{
"138":{
"Width":3,
"Shift":0,
"Value":196717},
"Value":196723},
"85":{
"91":{
"Width":2,
"Shift":-8,
"Value":196677},
"Value":196683},
"88":{
"94":{
"Width":1,
"Shift":-16,
"Value":196677},
"Value":196683},
"10":{
"Width":3,
@ -211,17 +211,17 @@
"Shift":0,
"Value":524313},
"102":{
"108":{
"Width":3,
"Shift":0,
"Value":327648},
"105":{
"111":{
"Width":3,
"Shift":0,
"Value":327648},
"100":{
"106":{
"Width":2,
"Shift":0,
"Value":327648},
@ -234,7 +234,7 @@
"63":{
"Width":2,
"Shift":0,
"Value":144478},
"Value":144487},
"35":{
"Width":2,
@ -251,7 +251,7 @@
"Shift":0,
"Value":524326},
"76":{
"82":{
"Width":2,
"Shift":0,
"Value":524313},
@ -299,49 +299,54 @@
"66":{
"Width":1,
"Shift":-16,
"Value":144478},
"Value":144487},
"67":{
"Width":1,
"Shift":-16,
"Value":524326},
"79":{
"85":{
"Width":1,
"Shift":-16,
"Value":524313},
"137":{
"143":{
"Width":3,
"Shift":0,
"Value":327648},
"194":{
"200":{
"Width":2,
"Shift":0,
"Value":144494},
"Value":144503},
"190":{
"196":{
"Width":3,
"Shift":0,
"Value":144470},
"220":{
"203":{
"Width":1,
"Shift":0,
"Value":144487},
"235":{
"Width":2,
"Shift":0,
"Value":524313},
"216":{
"231":{
"Width":3,
"Shift":0,
"Value":524288},
"240":{
"255":{
"Width":3,
"Shift":0,
"Value":524313},
"244":{
"259":{
"Width":3,
"Shift":0,
"Value":144470}},

45
SourceGen/SGTestData/Expected/20212-reloc-data_64tass.S
View File

@ -34,47 +34,49 @@ L30000 clc
nop
lda #$000f
ldx #_L80026 & $ffff
ldy #_L2345E & $ffff
mvn #(`_L2345E)+6,#`_L2345E
ldy #_L23467 & $ffff
mvn #(`_L23467)+6,#`_L23467
nop
_L30045 pea $0000
lda $0000,y
sta $0002,y
_L3004B pea $0000
pea $f000
pea _L80019 & $ffff
pea _L80019 >> 16
pea _L30045 & $ffff
pea _L30045 >> 8
_L30057 pea _L30045 >> 16
pea _L30057 & $ffff
pea $1045
pea _L3004B & $ffff
pea _L3004B >> 8
_L3005D pea _L3004B >> 16
pea _L3005D & $ffff
pea $104b
nop
jmp _L3006D
jmp _L30073
.word _L4FFE0 & $ffff
.long _L4FFE0
.long _L4FFE0
.byte $00
_L3006D phk
_L30073 phk
plb
lda #$0000
asl a
asl a
tax
lda @w_L30082 & $ffff,x
lda @w_L30088 & $ffff,x
pha
lda @w_L30080 & $ffff,x
lda @w_L30086 & $ffff,x
pha
beq _L30088
beq _L3008E
rts
_L30080 .byte $45
_L30086 .byte $4b
.byte $00
_L30082 .byte $03
_L30088 .byte $03
.byte $00
.long _L3006D
.long _L30073
.byte $00
_L30088 rts
_L3008E rts
;Segment 03: Kind=Data; Attrs=BankRel, Dynamic; Name='PosFFE0 '
.logical $04ffe0
@ -122,12 +124,15 @@ _L4FFE0 .long _L4FFE0
.as
.xs
_L23456 lda _L23456
jsr _L2346E
jsr _L23477
ldy #<_L23467
ora $3456
ora _L23456
rtl
_L2345E .fill 16,$00
_L23467 .fill 16,$00
_L2346E nop
_L23477 nop
rts
;Segment 05: Kind=Code; Attrs=AbsBank, Dynamic; Name='Bank8 '

45
SourceGen/SGTestData/Expected/20212-reloc-data_Merlin32.S
View File

@ -28,47 +28,49 @@ L30000 clc
nop
lda #$000f
ldx #:L80026
ldy #:L2345E
mvn #^:L2345E+$60000,#^:L2345E
ldy #:L23467
mvn #^:L23467+$60000,#^:L23467
nop
:L30045 pea $0000
lda $0000,y
sta $0002,y
:L3004B pea $0000
pea $f000
pea :L80019
pea ^:L80019
pea :L30045
pea >:L30045
:L30057 pea ^:L30045
pea :L30057
pea $1045
pea :L3004B
pea >:L3004B
:L3005D pea ^:L3004B
pea :L3005D
pea $104b
nop
jmp :L3006D
jmp :L30073
dw :L4FFE0
adr :L4FFE0
adr :L4FFE0
dfb $00
:L3006D phk
:L30073 phk
plb
lda #$0000
asl A
asl A
tax
lda: :L30082,x
lda: :L30088,x
pha
lda: :L30080,x
lda: :L30086,x
pha
beq :L30088
beq :L3008E
rts
:L30080 dfb $45
:L30086 dfb $4b
dfb $00
:L30082 dfb $03
:L30088 dfb $03
dfb $00
adr :L3006D
adr :L30073
dfb $00
:L30088 rts
:L3008E rts
;Segment 03: Kind=Data; Attrs=BankRel, Dynamic; Name='PosFFE0 '
org $04ffe0
@ -113,12 +115,15 @@ L30000 clc
org $023456
mx %11
:L23456 ldal :L23456
jsr :L2346E
jsr :L23477
ldy #<:L23467
ora $3456
oral :L23456
rtl
:L2345E ds 16
:L23467 ds 16
:L2346E nop
:L23477 nop
rts
;Segment 05: Kind=Code; Attrs=AbsBank, Dynamic; Name='Bank8 '

17
SourceGen/SGTestData/Expected/20212-reloc-data_acme.S
View File

@ -2,12 +2,13 @@
* = $0000
!pseudopc $030000 {
!hex 18fbe230af000003ea2256340222000008af563402ad5634a956a934a902af19
!hex 0008ad1900a919a900a908eac230a91900a90008a90800eaa90f00a22600a05e
!hex 34540208eaf40000f400f0f41900f40800f44500f40003f40300f45700f44510
!hex ea4c6d00e0ffe0ff04e0ff04004baba900000a0aaabd820048bd800048f00960
!hex 450003006d00030060e0ff0400000102030405060708090a0b0c0d0e0f101112
!hex 131415161718191a1b1c1d1e1f202122232425262728292a2b2c2d2e2faf5634
!hex 02206e346b00000000000000000000000000000000ea60af000008ad1900eaaf
!hex 000001af000002af000003af0000086b19000800563402008000100800546869
!hex 73206973206120746573742e0068656c6c6f2c20776f726c6421
!hex 0008ad1900a919a900a908eac230a91900a90008a90800eaa90f00a22600a067
!hex 34540208eab90000990200f40000f400f0f41900f40800f44b00f40003f40300
!hex f45d00f44b10ea4c7300e0ffe0ff04e0ff04004baba900000a0aaabd880048bd
!hex 860048f009604b0003007300030060e0ff0400000102030405060708090a0b0c
!hex 0d0e0f101112131415161718191a1b1c1d1e1f202122232425262728292a2b2c
!hex 2d2e2faf563402207734a0670d56340f5634026b000000000000000000000000
!hex 00000000ea60af000008ad1900eaaf000001af000002af000003af0000086b19
!hex 00080056340200800010080054686973206973206120746573742e0068656c6c
!hex 6f2c20776f726c6421
} ;!pseudopc

45
SourceGen/SGTestData/Expected/20212-reloc-data_cc65.S
View File

@ -33,47 +33,49 @@ L30000: clc
nop
lda #$000f
ldx #@L80026 & $ffff
ldy #@L2345E & $ffff
mvn #^@L2345E+6,#^@L2345E
ldy #@L23467 & $ffff
mvn #^@L23467+6,#^@L23467
nop
@L30045: pea $0000
lda $0000,y
sta $0002,y
@L3004B: pea $0000
pea $f000
pea @L80019 & $ffff
pea @L80019 >> 16
pea @L30045 & $ffff
pea @L30045 >> 8
@L30057: pea @L30045 >> 16
pea @L30057 & $ffff
pea $1045
pea @L3004B & $ffff
pea @L3004B >> 8
@L3005D: pea @L3004B >> 16
pea @L3005D & $ffff
pea $104b
nop
jmp @L3006D & $ffff
jmp @L30073 & $ffff
.word @L4FFE0 & $ffff
.faraddr @L4FFE0
.faraddr @L4FFE0
.byte $00
@L3006D: phk
@L30073: phk
plb
lda #$0000
asl A
asl A
tax
lda a:@L30082 & $ffff,x
lda a:@L30088 & $ffff,x
pha
lda a:@L30080 & $ffff,x
lda a:@L30086 & $ffff,x
pha
beq @L30088
beq @L3008E
rts
@L30080: .byte $45
@L30086: .byte $4b
.byte $00
@L30082: .byte $03
@L30088: .byte $03
.byte $00
.faraddr @L3006D
.faraddr @L30073
.byte $00
@L30088: rts
@L3008E: rts
;Segment 03: Kind=Data; Attrs=BankRel, Dynamic; Name='PosFFE0 '
; .segment "SEG001"
@ -122,12 +124,15 @@ L30000: clc
.a8
.i8
@L23456: lda @L23456
jsr @L2346E & $ffff
jsr @L23477 & $ffff
ldy #<@L23467
ora $3456
ora @L23456
rtl
@L2345E: .res 16,$00
@L23467: .res 16,$00
@L2346E: nop
@L23477: nop
rts
;Segment 05: Kind=Code; Attrs=AbsBank, Dynamic; Name='Bank8 '

4
SourceGen/SGTestData/Expected/20212-reloc-data_cc65.cfg
View File

@ -1,10 +1,10 @@
# 6502bench SourceGen generated linker script for 20212-reloc-data
MEMORY {
MAIN: file=%O, start=%S, size=65536;
# MEM000: file=%O, start=$30000, size=137;
# MEM000: file=%O, start=$30000, size=143;
# MEM001: file=%O, start=$4ffe0, size=32;
# MEM002: file=%O, start=$50000, size=20;
# MEM003: file=%O, start=$23456, size=26;
# MEM003: file=%O, start=$23456, size=35;
# MEM004: file=%O, start=$80000, size=54;
# MEM005: file=%O, start=$60000, size=13;
}

4
SourceGen/SGTestData/Source/20212-reloc-data-bank2.S
View File

@ -8,6 +8,10 @@
BANK2_START ENT
start ldal start
jsr later
ldy #BANK2_MOV_DST
ora $3456
oral $023456
rtl
BANK2_MOV_DST ENT

6
SourceGen/SGTestData/Source/20212-reloc-data-main.S
View File

@ -12,6 +12,7 @@ BANK8_ADDR EXT
BANK8_MOV_SRC EXT
ADDR_FFE0 EXT
; expected to start at $02/0000
REL ;generate relocatable code
start
@ -56,6 +57,11 @@ start
mvn #^BANK8_MOV_SRC,#^BANK2_MOV_DST
nop
; Test whether we're finding symbols for 16-bit address operands
; without reloc data.
lda: $0000,y
sta: $0002,y
check_pea
pea $0000
pea $f000