diff --git a/SourceGen/CodeAnalysis.cs b/SourceGen/CodeAnalysis.cs index 6b2e27c..6eaedb0 100644 --- a/SourceGen/CodeAnalysis.cs +++ b/SourceGen/CodeAnalysis.cs @@ -1383,6 +1383,11 @@ namespace SourceGen { if (offset < 1) { continue; } + // TODO(maybe): strictly speaking this is incorrect, because we're not verifying + // that the previous bytes are at adjacent addresses in memory. It's possible + // somebody did a PHA or PHK at the end of a chunk of code, then started + // assembling elsewhere with a PLB, and we'll mistakenly assign the wrong value. + // Seems unlikely, and the penalty for getting it "wrong" is slight. if (!mAnattribs[offset - 1].IsInstructionStart) { continue; } diff --git a/SourceGen/SGTestData/20032-labels-and-symbols.dis65 b/SourceGen/SGTestData/20032-labels-and-symbols.dis65 index c6af906..444cc0d 100644 --- a/SourceGen/SGTestData/20032-labels-and-symbols.dis65 +++ b/SourceGen/SGTestData/20032-labels-and-symbols.dis65 @@ -1,6 +1,6 @@ ### 6502bench SourceGen dis65 v1.0 ### { -"_ContentVersion":3, +"_ContentVersion":4, "FileDataLength":695, "FileDataCrc32":1242388944, "ProjectProps":{ @@ -14,7 +14,9 @@ "DefaultTextScanMode":"LowHighAscii", "MinCharsForString":4, "SeekNearbyTargets":true, -"SmartPlpHandling":true}, +"UseRelocData":false, +"SmartPlpHandling":true, +"SmartPlbHandling":true}, "PlatformSymbolFileIdentifiers":["PROJ:20030-labels-and-symbols.sym65", "RT:TestData/TestSyms.sym65"], @@ -1163,4 +1165,12 @@ "Visualizations":[], "VisualizationAnimations":[], "VisualizationSets":{ -}} +}, + +"RelocList":{ +}, + +"DbrValues":{ +"279":{ +"FollowPbr":true, +"Bank":0}}} diff --git a/SourceGen/SGTestData/20052-branches-and-banks.dis65 b/SourceGen/SGTestData/20052-branches-and-banks.dis65 index c29fd16..58e5da9 100644 --- a/SourceGen/SGTestData/20052-branches-and-banks.dis65 +++ b/SourceGen/SGTestData/20052-branches-and-banks.dis65 @@ -14,7 +14,9 @@ "DefaultTextScanMode":"LowHighAscii", "MinCharsForString":4, "SeekNearbyTargets":true, -"SmartPlpHandling":true}, +"UseRelocData":false, +"SmartPlpHandling":true, +"SmartPlbHandling":false}, "PlatformSymbolFileIdentifiers":["PROJ:20050-branches-and-banks.sym65"], "ExtensionScriptFileIdentifiers":[], @@ -272,4 +274,18 @@ "VisualizationSets":{ }, -"RelocList":null} +"RelocList":{ +}, + +"DbrValues":{ +"86":{ +"FollowPbr":true, +"Bank":0}, + +"11":{ +"FollowPbr":true, +"Bank":0}, + +"54":{ +"FollowPbr":true, +"Bank":0}}} diff --git a/SourceGen/SGTestData/20222-data-bank b/SourceGen/SGTestData/20222-data-bank new file mode 100644 index 0000000..5d47d67 Binary files /dev/null and b/SourceGen/SGTestData/20222-data-bank differ diff --git a/SourceGen/SGTestData/20222-data-bank.dis65 b/SourceGen/SGTestData/20222-data-bank.dis65 new file mode 100644 index 0000000..0587f2a --- /dev/null +++ b/SourceGen/SGTestData/20222-data-bank.dis65 @@ -0,0 +1,139 @@ +### 6502bench SourceGen dis65 v1.0 ### +{ +"_ContentVersion":4, +"FileDataLength":153, +"FileDataCrc32":-310531540, +"ProjectProps":{ +"CpuName":"65816", +"IncludeUndocumentedInstr":false, +"TwoByteBrk":false, +"EntryFlags":32702671, +"AutoLabelStyle":"Simple", +"AnalysisParams":{ +"AnalyzeUncategorizedData":true, +"DefaultTextScanMode":"LowHighAscii", +"MinCharsForString":4, +"SeekNearbyTargets":true, +"UseRelocData":false, +"SmartPlpHandling":true, +"SmartPlbHandling":true}, + +"PlatformSymbolFileIdentifiers":[], +"ExtensionScriptFileIdentifiers":[], +"ProjectSyms":{ +}}, + +"AddressMap":[{ +"Offset":0, +"Addr":4096}, + +{ +"Offset":64, +"Addr":139264}, + +{ +"Offset":114, +"Addr":208896}, + +{ +"Offset":127, +"Addr":208928}, + +{ +"Offset":137, +"Addr":147456}], +"TypeHints":[{ +"Low":0, +"High":0, +"Hint":"Code"}, + +{ +"Low":60, +"High":60, +"Hint":"Code"}, + +{ +"Low":110, +"High":110, +"Hint":"Code"}], +"StatusFlagOverrides":{ +}, + +"Comments":{ +}, + +"LongComments":{ +}, + +"Notes":{ +}, + +"UserLabels":{ +"64":{ +"Label":"bank2", +"Value":139264, +"Source":"User", +"Type":"GlobalAddr", +"LabelAnno":"None"}, + +"114":{ +"Label":"bank3", +"Value":208896, +"Source":"User", +"Type":"GlobalAddr", +"LabelAnno":"None"}, + +"0":{ +"Label":"start", +"Value":4096, +"Source":"User", +"Type":"GlobalAddr", +"LabelAnno":"None"}, + +"112":{ +"Label":"bank2addr", +"Value":139312, +"Source":"User", +"Type":"GlobalAddr", +"LabelAnno":"None"}}, + +"OperandFormats":{ +"58":{ +"Length":2, +"Format":"NumericLE", +"SubFormat":"Address", +"SymbolRef":null}, + +"61":{ +"Length":3, +"Format":"NumericLE", +"SubFormat":"Address", +"SymbolRef":null}, + +"112":{ +"Length":2, +"Format":"NumericLE", +"SubFormat":"Address", +"SymbolRef":null}, + +"135":{ +"Length":2, +"Format":"NumericLE", +"SubFormat":"Address", +"SymbolRef":null}}, + +"LvTables":{ +}, + +"Visualizations":[], +"VisualizationAnimations":[], +"VisualizationSets":{ +}, + +"RelocList":{ +}, + +"DbrValues":{ +"114":{ +"FollowPbr":false, +"Bank":2}}} diff --git a/SourceGen/SGTestData/Expected/20222-data-bank_64tass.S b/SourceGen/SGTestData/Expected/20222-data-bank_64tass.S new file mode 100644 index 0000000..b1522c2 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20222-data-bank_64tass.S @@ -0,0 +1,106 @@ + .cpu "65816" +* = $1000 + .as + .xs +start clc + xce + sep #$30 + lda start + lda $2000 + phk + plb + lda start + lda $2000 + lda #$02 + pha + plb + lda $1000 + lda bank2 & $ffff + ldx #$08 + tax + pha + plb + jsl bank2 + jsl L24000 + lda #$02 + pha + plb + jsl bank3 + phk + plb + bit start + jml L2400F + +L103A .word _L103C + +_L103C rts + +L103D .long L2202E + + .logical $022000 +bank2 lda bank2 + lda bank2 & $ffff + ldx #$00 + jsr _L2202B + jsr _L22025 + jsr _L22028 + nop + lda #$03 + pha + plb + lda L33028 & $ffff + rep #$30 + .al + .xl + lda #$00a9 + pha + plb + plb + sep #$30 + .as + .xs + rtl + +_L22025 jmp (L103A) + +_L22028 jml [L103D] + +_L2202B jmp (bank2addr,x) + +L2202E nop + rts + +bank2addr .word L2202E & $ffff + + .here + .logical $033000 +bank3 lda bank3 + lda bank2 & $ffff + jsr _L33020 + beq _L33024 + phk + .here + .logical $033020 +_L33020 plb + nop + bra _L33024 + +_L33024 lda $2030 + rtl + +L33028 .word L33028 & $ffff + + .here + .logical $024000 +L24000 lda L24000 + phb + phk + plb + lda bank2 & $ffff + lda $3000 + plb + rtl + +L2400F rts + + .here diff --git a/SourceGen/SGTestData/Expected/20222-data-bank_Merlin32.S b/SourceGen/SGTestData/Expected/20222-data-bank_Merlin32.S new file mode 100644 index 0000000..cef0f8d --- /dev/null +++ b/SourceGen/SGTestData/Expected/20222-data-bank_Merlin32.S @@ -0,0 +1,97 @@ + org $1000 +start clc + xce + sep #$30 + lda start + lda $2000 + phk + plb + lda start + lda $2000 + lda #$02 + pha + plb + lda $1000 + lda bank2 + ldx #$08 + tax + pha + plb + jsl bank2 + jsl L24000 + lda #$02 + pha + plb + jsl bank3 + phk + plb + bit start + jml L2400F + +L103A dw :L103C + +:L103C rts + +L103D adr L2202E + + org $022000 +bank2 ldal bank2 + lda bank2 + ldx #$00 + jsr :L2202B + jsr :L22025 + jsr :L22028 + nop + lda #$03 + pha + plb + lda L33028 + rep #$30 + mx %00 + lda #$00a9 + pha + plb + plb + sep #$30 + mx %11 + rtl + +:L22025 jmp (L103A) + +:L22028 jml [L103D] + +:L2202B jmp (bank2addr,x) + +L2202E nop + rts + +bank2addr dw L2202E + + org $033000 +bank3 ldal bank3 + lda bank2 + jsr :L33020 + beq :L33024 + phk + org $033020 +:L33020 plb + nop + bra :L33024 + +:L33024 lda $2030 + rtl + +L33028 dw L33028 + + org $024000 +L24000 ldal L24000 + phb + phk + plb + lda bank2 + lda $3000 + plb + rtl + +L2400F rts + diff --git a/SourceGen/SGTestData/Expected/20222-data-bank_acme.S b/SourceGen/SGTestData/Expected/20222-data-bank_acme.S new file mode 100644 index 0000000..d80b9d3 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20222-data-bank_acme.S @@ -0,0 +1,9 @@ +;ACME can't handle 65816 code that lives outside bank zero +* = $0000 + !pseudopc $1000 { + !hex 18fbe230ad0010ad00204babad0010ad0020a90248abad0010ad0020a208aa48 + !hex ab2200200222004002a90248ab220030034bab2c00105c0f40023c10602e2002 + !hex af002002ad0020a200202b20202520202820eaa90348abad2830c230a9a90048 + !hex ababe2306b6c3a10dc3d107c3020ea602e20af003003ad0020202030f0184bab + !hex ea8000ad30206b2830af0040028b4babad0020ad0030ab6b60 + } ;!pseudopc diff --git a/SourceGen/SGTestData/Expected/20222-data-bank_cc65.S b/SourceGen/SGTestData/Expected/20222-data-bank_cc65.S new file mode 100644 index 0000000..726c682 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20222-data-bank_cc65.S @@ -0,0 +1,107 @@ + .setcpu "65816" +; .segment "SEG000" + .org $1000 + .a8 + .i8 +start: clc + xce + sep #$30 + lda start + lda $2000 + phk + plb + lda start + lda $2000 + lda #$02 + pha + plb + lda $1000 + lda bank2 & $ffff + ldx #$08 + tax + pha + plb + jsl bank2 + jsl L24000 + lda #$02 + pha + plb + jsl bank3 + phk + plb + bit start + jml L2400F + +L103A: .word @L103C + +@L103C: rts + +L103D: .faraddr L2202E + +; .segment "SEG001" + .org $022000 +bank2: lda bank2 + lda bank2 & $ffff + ldx #$00 + jsr @L2202B & $ffff + jsr @L22025 & $ffff + jsr @L22028 & $ffff + nop + lda #$03 + pha + plb + lda L33028 & $ffff + rep #$30 + .a16 + .i16 + lda #$00a9 + pha + plb + plb + sep #$30 + .a8 + .i8 + rtl + +@L22025: jmp (L103A) + +@L22028: jml [L103D] + +@L2202B: jmp (bank2addr & $ffff,x) + +L2202E: nop + rts + +bank2addr: .word L2202E & $ffff + +; .segment "SEG002" + .org $033000 +bank3: lda bank3 + lda bank2 & $ffff + jsr @L33020 & $ffff + beq @L33024 + phk +; .segment "SEG003" + .org $033020 +@L33020: plb + nop + bra @L33024 + +@L33024: lda $2030 + rtl + +L33028: .word L33028 & $ffff + +; .segment "SEG004" + .org $024000 +L24000: lda L24000 + phb + phk + plb + lda bank2 & $ffff + lda $3000 + plb + rtl + +L2400F: rts + diff --git a/SourceGen/SGTestData/Expected/20222-data-bank_cc65.cfg b/SourceGen/SGTestData/Expected/20222-data-bank_cc65.cfg new file mode 100644 index 0000000..7a2c4d9 --- /dev/null +++ b/SourceGen/SGTestData/Expected/20222-data-bank_cc65.cfg @@ -0,0 +1,19 @@ +# 6502bench SourceGen generated linker script for 20222-data-bank +MEMORY { + MAIN: file=%O, start=%S, size=65536; +# MEM000: file=%O, start=$1000, size=64; +# MEM001: file=%O, start=$22000, size=50; +# MEM002: file=%O, start=$33000, size=13; +# MEM003: file=%O, start=$33020, size=10; +# MEM004: file=%O, start=$24000, size=16; +} +SEGMENTS { + CODE: load=MAIN, type=rw; +# SEG000: load=MEM000, type=rw; +# SEG001: load=MEM001, type=rw; +# SEG002: load=MEM002, type=rw; +# SEG003: load=MEM003, type=rw; +# SEG004: load=MEM004, type=rw; +} +FEATURES {} +SYMBOLS {} diff --git a/SourceGen/SGTestData/Source/20222-data-bank.S b/SourceGen/SGTestData/Source/20222-data-bank.S index dc410cd..6b00b55 100644 --- a/SourceGen/SGTestData/Source/20222-data-bank.S +++ b/SourceGen/SGTestData/Source/20222-data-bank.S @@ -2,6 +2,8 @@ ; See the LICENSE.txt file for distribution terms (Apache 2.0). ; ; Assembler: Merlin 32 +; +; "Smart PLB" should be enabled. org $1000 @@ -11,31 +13,33 @@ start sep #$30 mx %11 - lda start - lda bank2 + lda start ;initial offset has B=K + lda bank2 ;(should be hex) phk - plb + plb ;smart PLB should set B=K lda start - lda bank2 + lda bank2 ;(should be hex) lda #$02 pha - plb ;EDIT: set DBR=$02 - lda start + plb ;smart PLB should set B=$02 + lda start ;(should be hex) lda bank2 - lda #$08 + ldx #$08 + tax pha plb ;EDIT: set DBR=$08 jsl bank2 + jsl bank2_redux lda #$02 pha plb ;EDIT: set DBR=$02 jsl bank3 - phk + phk ;smart PLB should set B=K plb bit start @@ -43,7 +47,7 @@ start code2bz dw snippet ;EDIT: format as 16-bit address -snippet rts +snippet rts ;EDIT: code hint code2zero adr code2b ;EDIT: format as 24-bit address @@ -53,6 +57,7 @@ code2zero org $022000 bank2 ldal bank2 ;EDIT: set DBR=$08 + lda bank2 ;should become hex ldx #$00 jsr code2a jsr :call2bz @@ -61,9 +66,19 @@ bank2 lda #$03 pha - plb ;EDIT: set DBR=$03 + plb ;smart PLB should set B=$03 lda bank3dat +; try to fake out the "smart PLB" code + rep #$30 + mx %00 + lda #$00a9 + pha + plb + plb + sep #$30 + mx %11 + rtl :call2bz @@ -74,7 +89,7 @@ bank2 code2a jmp (bank2addr,x) ;both addresses formed with K code2b - nop + nop ;EDIT: code hint rts bank2addr @@ -84,6 +99,7 @@ bank2addr org $033000 bank3 ldal bank3 ;EDIT: set DBR=$02 + lda bank2 jsr :post_plb beq :skip_mayhem ; Test PHK/PLB with an address shift in the middle. Not really something @@ -100,7 +116,19 @@ bank3 rtl bank3dat - dw bank3dat + dw bank3dat ;EDIT: format as address + + + org $024000 +bank2_redux + ldal bank2_redux + phb + phk + plb + lda bank2 + lda bank3 ;should be hex + plb + rtl alldone rts