mirror of
https://github.com/fadden/6502bench.git
synced 2024-08-14 18:28:57 +00:00
d3e00b2342
The $Cxxx I/O locations are mapped into banks $E0/E1, and are usually
configured to appear in banks $00/01 as well. Direct access to
locations in banks $E0/E1 is common in 16-bit code, but we only had
definitions for $E0.
This adds a clone of definitions for $E1, and renames the symbols
to be _E0/_E1 instead of _GS.
This can also be solved with MULTI_MASK, but that will always use
$E0 as the base address, so references to $E1/Cxxx will have a large
adjustment added ("+$10000"), which is kind of ugly.
Note we still don't have definitions for $01/Cxxx. I'll add those
if I run into them in 16-bit code. (That might be a reasonable use
of MULTI_MASK; feels less ugly somehow.)
137 lines
6.6 KiB
Plaintext
137 lines
6.6 KiB
Plaintext
; Copyright 2020 faddenSoft. All Rights Reserved.
|
|
; See the LICENSE.txt file for distribution terms (Apache 2.0).
|
|
;
|
|
; Sources:
|
|
; NiftyList, by Dave Lyons
|
|
; Various Apple II reference materials found online
|
|
|
|
*SYNOPSIS Symbols for E0/Cxxx I/O locations
|
|
|
|
;
|
|
; This is just the list from Cxxx-IO.sym65, with the addresses in bank $e0
|
|
; and "_E0" appended to the symbol names.
|
|
;
|
|
KBD_E0 < $E0C000 ;R last key pressed + 128
|
|
CLR80COL_E0 > $E0C000 ;W use $C002-C005 for aux mem (80STOREOFF)
|
|
SET80COL_E0 @ $E0C001 ;W use PAGE2 for aux mem (80STOREON)
|
|
RDMAINRAM_E0 @ $E0C002 ;W if 80STORE off: read main mem $0200-BFFF
|
|
RDCARDRAM_E0 @ $E0C003 ;W if 80STORE off: read aux mem $0200-BFFF
|
|
WRMAINRAM_E0 @ $E0C004 ;W if 80STORE off: write main mem $0200-BFFF
|
|
WRCARDRAM_E0 @ $E0C005 ;W if 80STORE off: write aux mem $0200-BFFF
|
|
SETSLOTCXROM_E0 @ $E0C006 ;W use peripheral ROM ($C100-CFFF)
|
|
SETINTCXROM_E0 @ $E0C007 ;W use internal ROM ($C100-CFFF)
|
|
SETSTDZP_E0 @ $E0C008 ;W use main stack and zero page
|
|
SETALTZP_E0 @ $E0C009 ;W use aux stack and zero page
|
|
SETINTC3ROM_E0 @ $E0C00A ;W use internal slot 3 ROM
|
|
SETSLOTC3ROM_E0 @ $E0C00B ;W use external slot 3 ROM
|
|
CLR80VID_E0 @ $E0C00C ;W disable 80-column display mode
|
|
SET80VID_E0 @ $E0C00D ;W enable 80-column display mode
|
|
CLRALTCHAR_E0 @ $E0C00E ;W use primary char set
|
|
SETALTCHAR_E0 @ $E0C00F ;W use alternate char set
|
|
KBDSTRB_E0 @ $E0C010 ;RW keyboard strobe
|
|
RDLCBNK2_E0 @ $E0C011 ;R bit 7: reading from LC bank 2 ($Dx)?
|
|
RDLCRAM_E0 @ $E0C012 ;R bit 7: reading from LC RAM?
|
|
RDRAMRD_E0 @ $E0C013 ;R bit 7: reading from aux/alt 48K?
|
|
RDRAMWRT_E0 @ $E0C014 ;R bit 7: writing to aux/alt 48K?
|
|
RDCXROM_E0 @ $E0C015 ;R bit 7: using internal slot ROM?
|
|
RDALTZP_E0 @ $E0C016 ;R bit 7: using alt zero page, stack, & LC?
|
|
RDC3ROM_E0 @ $E0C017 ;R bit 7: using external (slot 3) ROM?
|
|
RD80COL_E0 @ $E0C018 ;R bit 7: 80STORE is on?
|
|
RDVBLBAR_E0 @ $E0C019 ;R bit 7: not VBL (VBL signal is low)?
|
|
RDTEXT_E0 @ $E0C01A ;R bit 7: using text mode?
|
|
RDMIX_E0 @ $E0C01B ;R bit 7: using mixed mode?
|
|
RDPAGE2_E0 @ $E0C01C ;R bit 7: using page 2?
|
|
RDHIRES_E0 @ $E0C01D ;R bit 7: using hi-res graphics?
|
|
ALTCHARSET_E0 @ $E0C01E ;R bit 7: using alt char set?
|
|
RD80VID_E0 @ $E0C01F ;R bit 7: using 80 columns?
|
|
TAPEOUT_E0 @ $E0C020 ;RW toggle caseette tape output
|
|
MONOCOLOR_E0 @ $E0C021 ;W color/mono
|
|
TBCOLOR_E0 @ $E0C022 ;RW screen color (low is BG, high is FG)
|
|
VGCINT_E0 @ $E0C023 ;R VGC interrupts
|
|
MOUSEDATA_E0 @ $E0C024 ;R mouse data: high bit is button
|
|
KEYMODREG_E0 @ $E0C025 ;R modifier key state
|
|
DATAREG_E0 @ $E0C026 ;RW ADB command/data
|
|
KMSTATUS_E0 @ $E0C027 ;RW ADB status
|
|
ROMBANK_E0 @ $E0C028 ;RW ROM bank select (IIc Plus)
|
|
NEWVIDEO_E0 @ $E0C029 ;RW video select (SHR)
|
|
LANGSEL_E0 @ $E0C02B ;RW ROM bank select
|
|
CHARROM_E0 @ $E0C02C ;R addr for character ROM test
|
|
SLTROMSEL_E0 @ $E0C02D ;RW slot vs. ROM selection
|
|
VERTCNT_E0 @ $E0C02E ;R read video counter bits (V5-VB)
|
|
HORIZCNT_E0 @ $E0C02F ;R read video counter bits (VA-H0)
|
|
SPKR_E0 @ $E0C030 ;RW toggle speaker
|
|
DISKREG_E0 @ $E0C031 ;RW disk interface
|
|
SCANINT_E0 @ $E0C032 ;W VGC interrupt clear
|
|
CLOCKDATA_E0 @ $E0C033 ;RW battery RAM interface
|
|
CLOCKCTL_E0 @ $E0C034 ;RW bits 0-3 = border color
|
|
SHADOW_E0 @ $E0C035 ;RW inhibit shadowing
|
|
CYAREG_E0 @ $E0C036 ;RW Configure Your Apple
|
|
DMAREG_E0 @ $E0C037 ;RW
|
|
SCCBREG_E0 @ $E0C038 ;RW SCC command channel B
|
|
SCCAREG_E0 @ $E0C039 ;RW SCC command channel A
|
|
SCCBDATA_E0 @ $E0C03A ;RW SCC data channel B
|
|
SCCADATA_E0 @ $E0C03B ;RW SCC data channel A
|
|
SOUNDCTL_E0 @ $E0C03C ;RW sound settings (0-3=volume)
|
|
SOUNDDATA_E0 @ $E0C03D ;RW sound data
|
|
SOUNDADRL_E0 @ $E0C03E ;RW low pointer
|
|
SOUNDADRH_E0 @ $E0C03F ;RW high pointer
|
|
STROBE_E0 @ $E0C040 ;R game I/O strobe
|
|
INTEN_E0 @ $E0C041 ;RW read VBL interrupt
|
|
|
|
MMDELTAX_E0 @ $E0C044 ;R mouse delta movement X
|
|
MMDELTAY_E0 @ $E0C045 ;R mouse delta movement Y
|
|
DIAGTYPE_E0 @ $E0C046 ;W self-test diagnostics
|
|
CLRVBLINT_E0 @ $E0C047 ;W clear VBL interrupt
|
|
CLRXYINT_E0 @ $E0C048 ;W clear XY interrupt
|
|
|
|
EMUBYTE_E0 @ $E0C04F ;RW used by emulators to identify themselves
|
|
TXTCLR_E0 @ $E0C050 ;RW display graphics
|
|
TXTSET_E0 @ $E0C051 ;RW display text
|
|
MIXCLR_E0 @ $E0C052 ;RW display full screen
|
|
MIXSET_E0 @ $E0C053 ;RW display split screen
|
|
TXTPAGE1_E0 @ $E0C054 ;RW display page 1
|
|
TXTPAGE2_E0 @ $E0C055 ;RW display page 2 (or read/write aux mem)
|
|
LORES_E0 @ $E0C056 ;RW display lo-res graphics
|
|
HIRES_E0 @ $E0C057 ;RW display hi-res graphics
|
|
SETAN0_E0 @ $E0C058 ;RW annunciator 0 off
|
|
CLRAN0_E0 @ $E0C059 ;RW annunciator 0 on
|
|
SETAN1_E0 @ $E0C05A ;RW annunciator 1 off
|
|
CLRAN1_E0 @ $E0C05B ;RW annunciator 1 on
|
|
SETAN2_E0 @ $E0C05C ;RW annunciator 2 off
|
|
CLRAN2_E0 @ $E0C05D ;RW annunciator 2 on
|
|
SETAN3_E0 @ $E0C05E ;RW annunciator 3 off
|
|
SETDHIRES_E0 = $E0C05E ;W if IOUDIS set, turn on double hi-res
|
|
CLRAN3_E0 @ $E0C05F ;RW annunciator 3 on
|
|
CLRDHIRES_E0 = $E0C05F ;W if IOUDIS set, turn off double hi-res
|
|
TAPEIN_E0 @ $E0C060 ;R read cassette input
|
|
BUTN3_E0 = $E0C060 ;R switch input 3
|
|
BUTN0_E0 @ $E0C061 ;R switch input 0 / open-apple
|
|
BUTN1_E0 @ $E0C062 ;R switch input 1 / closed-apple
|
|
BUTN2_E0 @ $E0C063 ;R switch input 2 / shift key
|
|
PADDL0_E0 @ $E0C064 ;R analog input 0
|
|
PADDL1_E0 @ $E0C065 ;R analog input 1
|
|
PADDL2_E0 @ $E0C066 ;R analog input 2
|
|
PADDL3_E0 @ $E0C067 ;R analog input 3
|
|
STATEREG_E0 @ $E0C068 ;RW address state
|
|
|
|
TESTREG_E0 @ $E0C06D ;test mode
|
|
CLTRM_E0 @ $E0C06E ;clear test mode
|
|
ENTM_E0 @ $E0C06F ;enable test mode
|
|
PTRIG_E0 @ $E0C070 ;RW analog input reset
|
|
|
|
RDIOUDIS_E0 < $E0C07E ;R status of IOU disabling
|
|
SETIOUDIS_E0 > $E0C07E ;W disable IOU
|
|
RDDHIRES_E0 < $E0C07F ;R status of double hi-res
|
|
CLRIOUDIS_E0 > $E0C07F ;W enable IOU
|
|
|
|
LCBANK2_RW_E0 @ $E0C080 ;RW read RAM bank 2, write off
|
|
ROMIN_E0 @ $E0C081 ;RWx2 read ROM, write RAM bank 2
|
|
ROMIN_RO_E0 @ $E0C082 ;RW read ROM, no write
|
|
LCBANK2_E0 @ $E0C083 ;RWx2 read/write RAM bank 2
|
|
LCBANK1_RW_E0 @ $E0C088 ;RW read RAM bank 1, write off
|
|
ROMIN1_E0 @ $E0C089 ;RWx2 read ROM, write RAM bank 1
|
|
ROMIN1_RO_E0 @ $E0C08A ;RW read ROM, no write
|
|
LCBANK1_E0 @ $E0C08B ;RWx2 read/write RAM bank 1
|
|
|
|
CLRROM_E0 @ $E0CFFF ;disable slot C8 ROM
|