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6502bench/SourceGen/SGTestData/Expected/1001-allops-zero-65816_64tass.S
Andy McFadden 32d1147eec Improve multi-encoding output in 64tass
Previously, we used the default character encoding from the project
properties to determine how strings and character constants in the
entire source file should be encoded.  Now we switch between
encodings as needed.  The default character encoding is no longer
relevant.

High ASCII is now an actual encoding, rather than acting like ASCII
that sometimes doesn't work.  Because we can do high ASCII character
operands with "| $80", we don't output a .enc to switch from ASCII
to high ASCII unless we need to generate a string.  (If we're
already in high ASCII mode, the "| $80" isn't required but won't
hurt anything.)

We now do a scan up front to see if ASCII or high ASCII is needed,
and only output the .cdefs for the encodings that are actually used.

The only gap in the matrix is high ASCII DCI strings -- the ".shift"
pseudo-op rejects text if the string doesn't start with the high
bit clear.
2019-08-21 13:46:05 -07:00

288 lines
5.6 KiB
ArmAsm

.cpu "65816"
* = $1000
.as
.xs
sec
xce
jsr L101F
jsr L10AB
jsr L10F2
jsr L1106
jsr L1109
jsr L112C
jsr L11F9
jsr L11FC
nop
nop
nop
brk
.byte $00
L101F ora ($00,x)
cop #$00
ora $00,s
tsb $00
ora $00
asl $00
ora [$00]
php
ora #$00
asl a
phd
tsb @w$0000
ora @w$0000
asl @w$0000
ora @l$000000
bpl L1041
L1041 ora ($00),y
ora ($00)
ora ($00,s),y
trb $00
ora $00,x
asl $00,x
ora [$00],y
clc
ora $0000,y
inc a
tcs
trb @w$0000
ora @w$0000,x
asl @w$0000,x
ora @l$000000,x
jsr $0000
and ($00,x)
jsl $000000
and $00,s
bit $00
and $00
rol $00
and [$00]
plp
and #$00
rol a
pld
bit @w$0000
and @w$0000
rol @w$0000
and @l$000000
bmi L1089
L1089 and ($00),y
and ($00)
and ($00,s),y
bit $00,x
and $00,x
rol $00,x
and [$00],y
sec
and $0000,y
dec a
tsc
bit @w$0000,x
and @w$0000,x
rol @w$0000,x
and @l$000000,x
rti
L10AB eor ($00,x)
.byte $42,$00
eor $00,s
mvp #$00,#$00
eor $00
lsr $00
eor [$00]
pha
eor #$00
lsr a
phk
jmp L10C2
L10C2 eor @w$0000
lsr @w$0000
eor @l$000000
bvc L10CE
L10CE eor ($00),y
eor ($00)
eor ($00,s),y
mvn #$00,#$00
eor $00,x
lsr $00,x
eor [$00],y
cli
eor $0000,y
phy
tcd
jml L10E7
L10E7 eor @w$0000,x
lsr @w$0000,x
eor @l$000000,x
rts
L10F2 adc ($00,x)
per $0ff6
adc $00,s
stz $00
adc $00
ror $00
adc [$00]
pla
adc #$00
ror a
rtl
L1106 jmp ($0000)
L1109 adc @w$0000
ror @w$0000
adc @l$000000
bvs L1115
L1115 adc ($00),y
adc ($00)
adc ($00,s),y
stz $00,x
adc $00,x
ror $00,x
adc [$00],y
sei
adc $0000,y
ply
tdc
jmp ($0000,x)
L112C adc @w$0000,x
ror @w$0000,x
adc @l$000000,x
bra L1138
L1138 sta ($00,x)
brl L113D
L113D sta $00,s
sty $00
sta $00
stx $00
sta [$00]
dey
bit #$00
txa
phb
sty @w$0000
sta @w$0000
stx @w$0000
sta @l$000000
bcc L115B
L115B sta ($00),y
sta ($00)
sta ($00,s),y
sty $00,x
sta $00,x
stx $00,y
sta [$00],y
tya
sta $0000,y
txs
txy
stz @w$0000
sta @w$0000,x
stz @w$0000,x
sta @l$000000,x
ldy #$00
lda ($00,x)
ldx #$00
lda $00,s
ldy $00
lda $00
ldx $00
lda [$00]
tay
lda #$00
tax
plb
ldy @w$0000
lda @w$0000
ldx @w$0000
lda @l$000000
bcs L11A0
L11A0 lda ($00),y
lda ($00)
lda ($00,s),y
ldy $00,x
lda $00,x
ldx $00,y
lda [$00],y
clv
lda $0000,y
tsx
tyx
ldy @w$0000,x
lda @w$0000,x
ldx @w$0000,y
lda @l$000000,x
cpy #$00
cmp ($00,x)
rep #$00
cmp $00,s
cpy $00
cmp $00
dec $00
cmp [$00]
iny
cmp #$00
dex
wai
cpy @w$0000
cmp @w$0000
dec @w$0000
cmp @l$000000
bne L11E5
L11E5 cmp ($00),y
cmp ($00)
cmp ($00,s),y
pei ($00)
cmp $00,x
dec $00,x
cmp [$00],y
cld
cmp $0000,y
phx
stp
L11F9 jml [$0000]
L11FC cmp @w$0000,x
dec @w$0000,x
cmp @l$000000,x
cpx #$00
sbc ($00,x)
sep #$00
sbc $00,s
cpx $00
sbc $00
inc $00
sbc [$00]
inx
sbc #$00
nop
xba
cpx @w$0000
sbc @w$0000
inc @w$0000
sbc @l$000000
beq L122A
L122A sbc ($00),y
sbc ($00)
sbc ($00,s),y
pea $0000
sbc $00,x
inc $00,x
sbc [$00],y
sed
sbc $0000,y
plx
xce
jsr ($0000,x)
sbc @w$0000,x
inc @w$0000,x
sbc @l$000000,x