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6502bench/SourceGen/SGTestData/Expected/10020-embedded-instructions_cc65.S
Andy McFadden 39b7b20144 ORG rework, part 1
This is the first step toward changing the address region map from a
linear list to a hierarchy.  See issue #107 for the plan.

The AddressMap class has been rewritten to support the new approach.
The rest of the project has been updated to conform to the new API,
but feature-wise is unchanged.  While the map class supports
nested regions with explicit lengths, the rest of the application
still assumes a series of non-overlapping regions with "floating"
lengths.

The Set Address dialog is currently non-functional.

All of the output for cc65 changed because generation of segment
comments has been removed.  Some of the output for ACME changed as
well, because we no longer follow "* = addr" with a redundant
pseudopc statement.  ACME and 65tass have similar approaches to
placing things in memory, and so now have similar implementations.
2021-09-16 17:02:19 -07:00

62 lines
1.2 KiB
ArmAsm

.setcpu "6502X"
.org $1000
jsr L100F
jsr L1017
jsr L101C
jsr L1046
jmp L1051
L100F: lda #$00
.byte $2c
@L1012: lda #$01
beq @L1012
rts
L1017: .byte $20
@L1018: rts
.byte $ea
bvs @L1018
L101C: .byte $2c
@L101D: .byte $2c
@L101E: .byte $2c
@L101F: .byte $2c
@L1020: .byte $2c
@L1021: .byte $2c
@L1022: .byte $2c
@L1023: .byte $2c
@L1024: .byte $2c
@L1025: nop
nop
asl A
bcc L101C
asl A
bcc @L101D
asl A
bcc @L101E
asl A
bcc @L101F
asl A
bcc @L1020
asl A
bcc @L1021
asl A
bcc @L1022
asl A
bcc @L1023
asl A
bcc @L1024
asl A
bcc @L1025
rts
L1046: .byte $2c
@L1047: nop
.byte $ad
@L1049: lda $00
asl A
bcc @L1047
asl A
bcc @L1049
L1051: .byte $ad