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The ZipChip GS register definitions can take advantage of the new I/O direction feature. Pulling them out into a .sym65 makes sense.
88 lines
3.6 KiB
Plaintext
88 lines
3.6 KiB
Plaintext
; Copyright 2018 faddenSoft. All Rights Reserved.
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; See the LICENSE.txt file for distribution terms (Apache 2.0).
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*SYNOPSIS ZipChip GS register definitions
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;
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; I got this from David Empson, who got it from Zip Technologies.
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;
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; ZipChip GS Special Registers Ex ZIP Technology, 12 October 1990
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;
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; Registers must be unlocked before they can be accessed (see $C05A).
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; Locking them will re-enable the annunciators.
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;
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; Writing to any I/O location $C058-$C05F (whether registers are locked or
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; unlocked) will reset delay in progress.
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;
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; $C058 R No operation
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;
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; $C058 W Write any value to force poweron/reset bit to COLD (forces next
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; reset to restore ZIP registers to defaults/switch settings).
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;
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; $C059 R/W 76543210
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; *....... Bank Switch Language Card cache disable=1/enable=0?
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; .*...... Paddle delay (5 ms) disable=0/enable=1 $C070/$C020
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; ..*..... External delay (5 ms) disable=0/enable=1
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; ...*.... Counter delay (5 ms) disable=0/enable=1 $C02E/$C07E
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; ....*... CPS follow disable=0/enable=1
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; .....*.. Last Reset warm? READ ONLY
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; ......*. Hardware DMA READ ONLY
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; .......* non-GS (0)/GS (1) READ ONLY
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;
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; $C05A R 76543210
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; ****.... Current ZIP Speed, 0=100%, F=6.25%, in 6.25% increments
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; ....1111
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;
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; $C05A W Write values as follows:
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; $5x Unlock ZIP registers (must write 4 times)
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; $Ax Lock ZIP registers
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; other Force ZIP to follow system clock (i.e. disable card)
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;
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; $C05B R 76543210
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; *....... 1msclk - clock with 1 ms period
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; .*...... cshupd - Tag data at $C05F updated (read $C05F to reset)
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; ..*..... Bank Switch Language Card cache (0), don't (1)
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; ...*.... Board disable - 0=enabled, 1=disabled
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; ....*... delay in effect (0=ZIP, 1=Slow)
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; .....*.. rombank (0/1) - not in development version
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; ......** Cache RAM size (00=8k, 01=16k, 10=32k, 11=64k)
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;
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; $C05B W Write any value to force ZIP to current speed (i.e. enable card)
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;
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; $C05C R/W 76543210
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; *******. Slot 7-1 delay enable (all slots 52-54 ms)
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; .......* Speaker delay enable (5 ms)
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;
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; $C05D R Current 65816 bank
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;
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; $C05D W 76543210
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; ****.... Set ZIP speed, 0=100%, F=6.25%, in 6.25% increments
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; ....**** Don't care
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;
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; $C05E R Read last Tag data written and force the next write to
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; create a trash tag value.
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;
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; $C05E W No operation
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;
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; $C05F R Read last Tag data written and reset cshupd. Note: apparently
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; any write to a ZIP register (unlocked) will clear cshupd, but cshupd says
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; that this location must be read.
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;
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; $C05F W No operation
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ZIP_Reset > $c058 ;W write any value to force poweron/reset bit to COLD
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ZIP_Options @ $c059 ;RW bit flags: paddle delay, CPS follow, etc.
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ZIP_Speed < $c05a ;R current ZIP speed in 6.25% increments
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ZIP_Lock > $c05a ;W $5* unlock (write 4x), $A* lock, other=disable
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ZIP_Status < $c05b ;R bit flags: status values
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ZIP_Enable > $c05b ;W write any value to enable card
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ZIP_SlotEnable @ $c05c ;RW bit flags: enable delay on slots and speaker
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ZIP_Bank < $c05d ;R current 65816 bank
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ZIP_SetSpeed > $c05d ;W set ZIP speed in 6.25% increments
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ZIP_Tag1 < $c05e ;R read last Tag written and force trash tag
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ZIP_Nop1 > $c05e ;W no-op with side-effects
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ZIP_Tag2 < $c05f ;R read last tag written and reset cshupd
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ZIP_Nop2 > $c05f ;W no-op with side-effects
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