mirror of
https://github.com/fadden/6502bench.git
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39b7b20144
This is the first step toward changing the address region map from a linear list to a hierarchy. See issue #107 for the plan. The AddressMap class has been rewritten to support the new approach. The rest of the project has been updated to conform to the new API, but feature-wise is unchanged. While the map class supports nested regions with explicit lengths, the rest of the application still assumes a series of non-overlapping regions with "floating" lengths. The Set Address dialog is currently non-functional. All of the output for cc65 changed because generation of segment comments has been removed. Some of the output for ACME changed as well, because we no longer follow "* = addr" with a redundant pseudopc statement. ACME and 65tass have similar approaches to placing things in memory, and so now have similar implementations.
276 lines
5.7 KiB
ArmAsm
276 lines
5.7 KiB
ArmAsm
.setcpu "65C02"
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.org $1000
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jsr L1014
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jsr L108A
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jsr L10C4
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jsr L10D8
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jsr L10F6
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nop
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nop
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nop
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brk
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.byte $00
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L1014: ora ($00,x)
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.byte $02,$00
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.byte $03
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tsb $00
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ora $00
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asl $00
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.byte $07
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php
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ora #$00
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asl A
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.byte $0b
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tsb a:$0000
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ora a:$0000
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asl a:$0000
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.byte $0f
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bpl @L1031
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@L1031: ora ($00),y
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ora ($00)
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.byte $13
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trb $00
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ora $00,x
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asl $00,x
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.byte $17
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clc
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ora $0000,y
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inc A
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.byte $1b
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trb a:$0000
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ora a:$0000,x
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asl a:$0000,x
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.byte $1f
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jsr $0000
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and ($00,x)
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.byte $22,$00
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.byte $23
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bit $00
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and $00
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rol $00
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.byte $27
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plp
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and #$00
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rol A
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.byte $2b
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bit a:$0000
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and a:$0000
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rol a:$0000
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.byte $2f
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bmi @L106D
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@L106D: and ($00),y
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and ($00)
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.byte $33
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bit $00,x
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and $00,x
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rol $00,x
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.byte $37
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sec
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and $0000,y
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dec A
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.byte $3b
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bit a:$0000,x
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and a:$0000,x
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rol a:$0000,x
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.byte $3f
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rti
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L108A: eor ($00,x)
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.byte $42,$00
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.byte $43
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.byte $44,$00
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eor $00
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lsr $00
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.byte $47
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pha
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eor #$00
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lsr A
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.byte $4b
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jmp @L109E
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@L109E: eor a:$0000
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lsr a:$0000
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.byte $4f
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bvc @L10A7
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@L10A7: eor ($00),y
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eor ($00)
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.byte $53
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.byte $54,$00
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eor $00,x
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lsr $00,x
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.byte $57
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cli
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eor $0000,y
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phy
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.byte $5b
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.byte $5c,$00,$00
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eor a:$0000,x
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lsr a:$0000,x
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.byte $5f
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rts
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L10C4: adc ($00,x)
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.byte $62,$00
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.byte $63
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stz $00
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adc $00
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ror $00
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.byte $67
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pla
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adc #$00
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ror A
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.byte $6b
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jmp ($0000)
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L10D8: adc a:$0000
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ror a:$0000
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.byte $6f
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bvs @L10E1
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@L10E1: adc ($00),y
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adc ($00)
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.byte $73
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stz $00,x
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adc $00,x
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ror $00,x
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.byte $77
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sei
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adc $0000,y
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ply
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.byte $7b
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jmp ($0000,x)
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L10F6: adc a:$0000,x
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ror a:$0000,x
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.byte $7f
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bra @L10FF
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@L10FF: sta ($00,x)
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.byte $82,$00
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.byte $83
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sty $00
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sta $00
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stx $00
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.byte $87
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dey
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bit #$00
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txa
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.byte $8b
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sty a:$0000
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sta a:$0000
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stx a:$0000
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.byte $8f
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bcc @L111C
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@L111C: sta ($00),y
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sta ($00)
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.byte $93
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sty $00,x
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sta $00,x
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stx $00,y
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.byte $97
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tya
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sta $0000,y
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txs
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.byte $9b
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stz a:$0000
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sta a:$0000,x
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stz a:$0000,x
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.byte $9f
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ldy #$00
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lda ($00,x)
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ldx #$00
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.byte $a3
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ldy $00
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lda $00
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ldx $00
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.byte $a7
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tay
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lda #$00
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tax
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.byte $ab
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ldy a:$0000
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lda a:$0000
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ldx a:$0000
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.byte $af
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bcs @L1157
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@L1157: lda ($00),y
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lda ($00)
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.byte $b3
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ldy $00,x
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lda $00,x
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ldx $00,y
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.byte $b7
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clv
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lda $0000,y
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tsx
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.byte $bb
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ldy a:$0000,x
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lda a:$0000,x
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ldx a:$0000,y
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.byte $bf
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cpy #$00
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cmp ($00,x)
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.byte $c2,$00
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.byte $c3
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cpy $00
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cmp $00
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dec $00
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.byte $c7
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iny
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cmp #$00
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dex
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.byte $cb
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cpy a:$0000
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cmp a:$0000
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dec a:$0000
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.byte $cf
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bne @L1192
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@L1192: cmp ($00),y
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cmp ($00)
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.byte $d3
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.byte $d4,$00
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cmp $00,x
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dec $00,x
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.byte $d7
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cld
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cmp $0000,y
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phx
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.byte $db
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.byte $dc,$00,$00
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cmp a:$0000,x
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dec a:$0000,x
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.byte $df
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cpx #$00
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sbc ($00,x)
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.byte $e2,$00
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.byte $e3
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cpx $00
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sbc $00
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inc $00
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.byte $e7
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inx
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sbc #$00
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nop
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.byte $eb
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cpx a:$0000
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sbc a:$0000
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inc a:$0000
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.byte $ef
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beq @L11CD
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@L11CD: sbc ($00),y
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sbc ($00)
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.byte $f3
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.byte $f4,$00
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sbc $00,x
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inc $00,x
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.byte $f7
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sed
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sbc $0000,y
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plx
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.byte $fb
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.byte $fc,$00,$00
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sbc a:$0000,x
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inc a:$0000,x
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.byte $ff
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