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<title>Instruction and Data Analysis - 6502bench SourceGen</title>
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<h1>6502bench SourceGen: Instruction and Data Analysis</h1>
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<p><a href="index.html">Back to index</a></p>
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<h2><a name="analysis-process">Analysis Process</a></h2>
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<p>Analysis of the file data is a complex multi-step process. Some
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changes to the project, such as adding a code entry point hint or
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changing the CPU selection, require a full re-analysis of instructions
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and data. Other changes, such as adding or removing a label, don't
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affect the code tracing and only require a re-analysis of the data areas.
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And some changes, such as editing a comment, only require a refresh
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of the displayed lines.</p>
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<p>It should be noted that none of the analysis results are stored in
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the project file. Only user-supplied data, such as the locations of
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code entry points and label definitions, is written to the file. This
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does create the possibility that two different users might get different
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results when opening the same project file with different versions of
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SourceGen, but these effects are expected to be minor.</p>
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<p>The analyzer has the following steps (see the <code>Analyze</code>
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method in <code>DisasmProject.cs</code>):</p>
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<ul>
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<li>Reset the symbol table.</li>
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<li>Merge platform symbols into the symbol table, loading the files
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in order.</li>
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<li>Merge project symbols into the symbol table, stomping on any
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platform symbols that conflict.</li>
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<li>Merge user label symbols into the table, stomping any previous
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entries.</li>
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<li>Run the code analyzer. The outcome of this is an array of analysis
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attributes, or "anattribs", with one entry per byte in the file.
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The Anattrib array tracks most of the state from here on. If we're
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doing a partial re-analysis, this step will just clone a copy of the
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Anattrib array that was made at this point in a previous run. (This
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step is described in more detail <a href="code-analysis">below</a>.)</li>
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<li>Apply user-specified labels to Anattribs.</li>
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<li>Apply user-specified format descriptors. These are the instruction
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and data operand formats.</li>
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<li>Run the data analyzer. This looks for patterns in uncategorized
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data, and connects instruction and data operands to target offsets.
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The "nearby label" stuff is handled here. All of the results are
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stored in the Anattribs array. (This step is described in more
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detail <a href="data-analysis">below</a>.)</li>
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<li>Remove hidden labels from the symbol table. These are user-specified
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labels that have been placed on offsets that are in the middle of an
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instruction or multi-byte data item. They can't be referenced, so we
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want to pull them out of the symbol table. (Remember, symbolic
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operands use "weak references", so a missing symbol just means the
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operand is shown as a hex value.)</li>
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<li>Resolve references to platform and project external symbols>
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This sets the operand symbol in Anattrib, and adds the symbol to
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the list that is displayed in .EQ directives.</li>
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<li>Generate cross-reference lists. This is done for file data and
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for any platform/project symbols that are referenced.</li>
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<li>In a debug build, some validity checks are performed.</li>
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</ul>
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<p>Once analysis is complete, a line-by-line display list is generated
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by walking through the annotated file data. Most of the actual strings
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aren't rendered until they're needed.</p>
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<h2><a name="code-analysis">Code Analysis</a></h2>
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<p>The code tracer walks through the instructions, examining them to
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determine where execution will proceed next. There are five possibilities
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for every instruction:</p>
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<ol>
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<li>Continue. Execution always continues at the next instruction.
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Examples: <code>LDA</code>, <code>STA</code>, <code>AND</code>,
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<code>NOP</code>.
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<li>Don't continue. The next instruction to be executed can't be
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determined from the file data, unless you're disassembling the
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system ROM. Examples: <code>RTS</code>, <code>BRK</code>.
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<li>Branch always. The operand specifies the next instruction address.
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Examples: <code>JMP</code>, <code>BRA</code>, <code>BRL</code>.
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<li>Branch sometimes. Execution may continue at the operand address,
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or may execute the following instruction. If we know the value of
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the flags in the processor status register, we can eliminate one
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possibility. Examples: <code>BCC</code>, <code>BEQ</code>,
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<code>BVS</code>.
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<li>Call subroutine. Execution will continue at the operand address,
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and is expected to also continue at the following instruction.
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Examples: <code>JSR</code>, <code>JSL</code>.
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</ol>
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<p>Branch targets are added to a list. When the current run of instructions
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is exhausted (i.e. a "don't continue" instruction is reached), the next
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target is pulled off of the list.</p>
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<p>The state of the processor status flags is recorded for every
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instruction. When execution proceeds to the next instruction or branches
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to a new address, the flags are merged with the flags at the new
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location. If one execution path through a given address has the flags
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in one state (say, the carry is clear), while another execution path
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sees a different state (carry is set), the merged flag is
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"indeterminate". Indeterminate values cannot become determinate through
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a merge, but can be set by an instruction.</p>
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<p>There can be multiple paths to a single address. If the analyzer
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sees that an instruction has been visited before, with an identical set
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of status flags, the analyzer stops pursuing that path.</p>
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<p>The analyzer must always know the width of immediate load instructions
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when examining 65816 code, but it's possible for the status flag values
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to be indeterminate. In such a situation, short registers are assumed.
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Similarly, if the carry flag is unknown when an <code>XCE</code> is
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performed, we assume a transition to emulation mode.</p>
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<p>There are three ways to set a definite value in a status flags:</p>
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<ol>
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<li>By specific instructions, like <code>SEC</code> or
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<code>CLD</code>.</li>
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<li>By immediate instructions. <code>LDA #$00</code> sets Z=1 and N=0.
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<code>ORA #$80</code> sets Z=0 and N=1.</li>
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<li>By inference. For example, if we see a <code>BCC</code> instruction,
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we know that the carry will be clear at the branch target address, and
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set at the following instruction. The instruction doesn't affect the
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value of the flag, but we know what the value is at either address.</li>
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</ol>
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<p>Self-modifying code can render spoil any of these, possibly requiring a
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status flag override to get correct disassembly.</p>
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<p>The instruction that is most likely to cause problems is <code>PLP</code>,
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which pulls the processor status flags off of the stack. SourceGen
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doesn't try to track stack contents, so it can't know what values may
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be pulled. In many cases the PLP appears not long after a PHP, so
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SourceGen will scan backward through the file to find the nearest PHP,
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and use the status flags from that. If no PHP can be found, then all
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flags are set to "indeterminate". (The boot loader in the Apple II 5.25"
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floppy disk controller is an example where SourceGen gets it wrong. The
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code does <code>CLC</code>/<code>PHP</code>, followed a bit later by the
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<code>PLP</code>, but it's actually using the stack to pass the carry
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flag around. Flagging the carry bit as indeterminate with a status flag
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override on the instruction following the PLP fixes things.)</p>
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<p>Some other things that the code analyzer can't handle:</p>
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<ul>
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<li>Jumping indirectly through an address outside the file, e.g.
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storing an address in zero-page memory and jumping through it.
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<li>Jumping to an address by pushing the location onto the stack,
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then executing an <code>RTS</code>.
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<li>Self-modifying code, e.g. overwriting a <code>JMP</code> instruction.
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</ul>
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<p>Sometimes the indirect jump targets are coming from a table of
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addresses in the file. If so, these can be formatted as addresses,
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and then the target locations hinted as code entry points.</p>
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<p>The 65816 adds an additional twist: 16-bit data access instructions
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use the data bank register ("B") to determine which bank to load from.
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SourceGen can't determine what the value is, so it currently assumes
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that it's equal to the program bank register ("K"). Handling this
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correctly will require improvements to the user interface.</p>
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<h2><a name="data-analysis">Data Analysis</a></h2>
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<p>The data analyzer performs two tasks. It matches operands with
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offsets, and it analyzes uncategorized data. Either or both of
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these can be disabled from the
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<a href="settings.html#project-props">project properties</a></p>
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<p>The data target analyzer examines every instruction and data operand
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to see if it's referring to an offset within the data file. If the
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target is within the file, and has a label, a weak symbolic reference
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to that label is added to the Anattrib array. If the target doesn't
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have a label, the analyzer will either use a nearby label, or generate
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a unique label and use that.</p>
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<p>While most of the "nearby label" logic can be disabled, targets that
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land in the middle of an instruction are always adjusted backward to
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the instruction start. This is necessary because labels are only visible
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if they're associated with the first (opcode) byte of an instruction.</p>
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<p>The uncategorized data analyzer tries to find ASCII strings and
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opportunities to use the ".FILL" instruction. It breaks the file into
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pieces, where contiguous regions hold nothing but data, are not split
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across a ".ORG" directive, are not interrupted by data, and do not
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contain anything that the user has chosen to format. Each region is
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scanned for matching patterns. If a match is found, a format entry
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is added to the Anattrib array. Otherwise, data is added as independent
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byte values.</p>
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