1
0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-12-11 02:49:22 +00:00
8bitworkshop/presets/verilog/Makefile

8 lines
175 B
Makefile
Raw Normal View History

check:
verilator --top-module frame_buffer_top --lint-only *.v
iverilog -tnull *.v
deps.dot:
grep \`include *.v | sed "s/:/ /g" | awk '{ print "\"" $1 "\" -> " $3 ";" }'