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8bitworkshop/test/cli/verilog/t_attr_parenstar.v

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2021-07-06 20:45:27 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
always @(*) begin
if (clk) begin end
end
always @(* ) begin
if (clk) begin end
end
// Not legal in some simulators, legal in others
// always @(* /*cmt*/ ) begin
// if (clk) begin end
// end
// Not legal in some simulators, legal in others
// always @(* // cmt
// ) begin
// if (clk) begin end
// end
always @ (*
) begin
if (clk) begin end
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule