mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-22 14:33:51 +00:00
23 lines
527 B
Coq
23 lines
527 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// A test of the +verilog2001ext+ and +verilog2005ext+ flags.
|
||
|
|
//
|
||
|
|
// This source code uses the uwire declaration, which is only valid in Verilog
|
||
|
|
// 2005.
|
||
|
|
//
|
||
|
|
// Compile only test, so no need for "All Finished" output.
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2012 by Jeremy Bennett.
|
||
|
|
// SPDX-License-Identifier: CC0-1.0
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/
|
||
|
|
// Inputs
|
||
|
|
clk
|
||
|
|
);
|
||
|
|
input clk;
|
||
|
|
|
||
|
|
uwire w; // Only in Verilog 2005
|
||
|
|
|
||
|
|
endmodule
|