mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-22 14:33:51 +00:00
32 lines
542 B
Coq
32 lines
542 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||
|
|
// any use, without warranty, 2006 by Wilson Snyder.
|
||
|
|
// SPDX-License-Identifier: CC0-1.0
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/
|
||
|
|
// Outputs
|
||
|
|
b,
|
||
|
|
// Inputs
|
||
|
|
clk, en, a
|
||
|
|
);
|
||
|
|
|
||
|
|
// bug1017
|
||
|
|
|
||
|
|
input clk;
|
||
|
|
|
||
|
|
input en;
|
||
|
|
input a[1];
|
||
|
|
output logic b[1];
|
||
|
|
|
||
|
|
always_ff @ (posedge clk) begin
|
||
|
|
b <= en ? a : b;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
$write("*-* All Finished *-*\n");
|
||
|
|
$finish;
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|