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24 lines
648 B
Coq
24 lines
648 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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localparam UNB = $;
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localparam int UNB2 = $;
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localparam SIX = 6;
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initial begin
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if ($bits($isunbounded(0)) !== 1) $stop;
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if ($isunbounded(0) !== 1'b0) $stop;
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if ($isunbounded(SIX) !== 0) $stop;
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if ($isunbounded($) !== 1) $stop;
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if ($isunbounded(UNB) !== 1) $stop;
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if ($isunbounded(UNB2) !== 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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