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8bitworkshop/presets/verilog/Makefile

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Makefile
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check:
verilator --top-module frame_buffer_top --lint-only *.v
iverilog -tnull *.v
deps.dot:
grep \`include *.v | sed "s/:/ /g" | awk '{ print "\"" $1 "\" -> " $3 ";" }'
2018-10-01 23:43:06 +00:00
%.bin: %.v
~/yosys/yosys -p "synth_ice40 -blif $*.blif" $*.v
arachne-pnr -d 1k -p icestick.pcf $*.blif -o $*.asc
icepack $*.asc $*.bin
#iceprog $*.bin