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28 lines
632 B
Coq
28 lines
632 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork
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// SPDX-License-Identifier: CC0-1.0
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module mod #(
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parameter real HZ = 0
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);
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//verilator no_inline_module
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initial begin
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if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop;
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if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop;
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end
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endmodule
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module t();
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mod #(.HZ(123.45)) mod1();
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mod #(.HZ(24.45)) mod2();
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initial begin
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if (mod1.HZ != 123.45) $stop;
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if (mod2.HZ != 24.45) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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