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201 lines
9.2 KiB
C
201 lines
9.2 KiB
C
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; VCS.H
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; Version 1.05, 13/November/2003
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VERSION_VCS = 105
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; THIS IS A PRELIMINARY RELEASE OF *THE* "STANDARD" VCS.H
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; THIS FILE IS EXPLICITLY SUPPORTED AS A DASM-PREFERRED COMPANION FILE
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; PLEASE DO *NOT* REDISTRIBUTE THIS FILE!
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;
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; This file defines hardware registers and memory mapping for the
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; Atari 2600. It is distributed as a companion machine-specific support package
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; for the DASM compiler. Updates to this file, DASM, and associated tools are
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; available at at http://www.atari2600.org/dasm
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;
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; Many thanks to the original author(s) of this file, and to everyone who has
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; contributed to understanding the Atari 2600. If you take issue with the
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; contents, or naming of registers, please write to me (atari2600@taswegian.com)
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; with your views. Please contribute, if you think you can improve this
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; file!
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;
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; Latest Revisions...
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; 1.05 13/NOV/2003 - Correction to 1.04 - now functions as requested by MR.
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; - Added VERSION_VCS equate (which will reflect 100x version #)
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; This will allow conditional code to verify VCS.H being
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; used for code assembly.
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; 1.04 12/NOV/2003 Added TIA_BASE_WRITE_ADDRESS and TIA_BASE_READ_ADDRESS for
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; convenient disassembly/reassembly compatibility for hardware
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; mirrored reading/writing differences. This is more a
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; readability issue, and binary compatibility with disassembled
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; and reassembled sources. Per Manuel Rotschkar's suggestion.
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; 1.03 12/MAY/2003 Added SEG segment at end of file to fix old-code compatibility
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; which was broken by the use of segments in this file, as
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; reported by Manuel Polik on [stella] 11/MAY/2003
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; 1.02 22/MAR/2003 Added TIMINT($285)
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; 1.01 Constant offset added to allow use for 3F-style bankswitching
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; - define TIA_BASE_ADDRESS as $40 for Tigervision carts, otherwise
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; it is safe to leave it undefined, and the base address will
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; be set to 0. Thanks to Eckhard Stolberg for the suggestion.
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; Note, may use -DLABEL=EXPRESSION to define TIA_BASE_ADDRESS
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; - register definitions are now generated through assignment
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; in uninitialised segments. This allows a changeable base
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; address architecture.
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; 1.0 22/MAR/2003 Initial release
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;-------------------------------------------------------------------------------
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; TIA_BASE_ADDRESS
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; The TIA_BASE_ADDRESS defines the base address of access to TIA registers.
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; Normally 0, the base address should (externally, before including this file)
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; be set to $40 when creating 3F-bankswitched (and other?) cartridges.
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; The reason is that this bankswitching scheme treats any access to locations
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; < $40 as a bankswitch.
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IFNCONST TIA_BASE_ADDRESS
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TIA_BASE_ADDRESS = 0
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ENDIF
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; Note: The address may be defined on the command-line using the -D switch, eg:
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; dasm.exe code.asm -DTIA_BASE_ADDRESS=$40 -f3 -v5 -ocode.bin
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; *OR* by declaring the label before including this file, eg:
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; TIA_BASE_ADDRESS = $40
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; include "vcs.h"
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; Alternate read/write address capability - allows for some disassembly compatibility
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; usage ; to allow reassembly to binary perfect copies). This is essentially catering
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; for the mirrored ROM hardware registers.
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; Usage: As per above, define the TIA_BASE_READ_ADDRESS and/or TIA_BASE_WRITE_ADDRESS
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; using the -D command-line switch, as required. If the addresses are not defined,
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; they defaut to the TIA_BASE_ADDRESS.
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IFNCONST TIA_BASE_READ_ADDRESS
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TIA_BASE_READ_ADDRESS = TIA_BASE_ADDRESS
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ENDIF
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IFNCONST TIA_BASE_WRITE_ADDRESS
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TIA_BASE_WRITE_ADDRESS = TIA_BASE_ADDRESS
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ENDIF
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;-------------------------------------------------------------------------------
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SEG.U TIA_REGISTERS_WRITE
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ORG TIA_BASE_WRITE_ADDRESS
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; DO NOT CHANGE THE RELATIVE ORDERING OF REGISTERS!
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VSYNC ds 1 ; $00 0000 00x0 Vertical Sync Set-Clear
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VBLANK ds 1 ; $01 xx00 00x0 Vertical Blank Set-Clear
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WSYNC ds 1 ; $02 ---- ---- Wait for Horizontal Blank
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RSYNC ds 1 ; $03 ---- ---- Reset Horizontal Sync Counter
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NUSIZ0 ds 1 ; $04 00xx 0xxx Number-Size player/missle 0
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NUSIZ1 ds 1 ; $05 00xx 0xxx Number-Size player/missle 1
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COLUP0 ds 1 ; $06 xxxx xxx0 Color-Luminance Player 0
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COLUP1 ds 1 ; $07 xxxx xxx0 Color-Luminance Player 1
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COLUPF ds 1 ; $08 xxxx xxx0 Color-Luminance Playfield
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COLUBK ds 1 ; $09 xxxx xxx0 Color-Luminance Background
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CTRLPF ds 1 ; $0A 00xx 0xxx Control Playfield, Ball, Collisions
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REFP0 ds 1 ; $0B 0000 x000 Reflection Player 0
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REFP1 ds 1 ; $0C 0000 x000 Reflection Player 1
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PF0 ds 1 ; $0D xxxx 0000 Playfield Register Byte 0
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PF1 ds 1 ; $0E xxxx xxxx Playfield Register Byte 1
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PF2 ds 1 ; $0F xxxx xxxx Playfield Register Byte 2
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RESP0 ds 1 ; $10 ---- ---- Reset Player 0
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RESP1 ds 1 ; $11 ---- ---- Reset Player 1
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RESM0 ds 1 ; $12 ---- ---- Reset Missle 0
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RESM1 ds 1 ; $13 ---- ---- Reset Missle 1
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RESBL ds 1 ; $14 ---- ---- Reset Ball
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AUDC0 ds 1 ; $15 0000 xxxx Audio Control 0
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AUDC1 ds 1 ; $16 0000 xxxx Audio Control 1
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AUDF0 ds 1 ; $17 000x xxxx Audio Frequency 0
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AUDF1 ds 1 ; $18 000x xxxx Audio Frequency 1
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AUDV0 ds 1 ; $19 0000 xxxx Audio Volume 0
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AUDV1 ds 1 ; $1A 0000 xxxx Audio Volume 1
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GRP0 ds 1 ; $1B xxxx xxxx Graphics Register Player 0
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GRP1 ds 1 ; $1C xxxx xxxx Graphics Register Player 1
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ENAM0 ds 1 ; $1D 0000 00x0 Graphics Enable Missle 0
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ENAM1 ds 1 ; $1E 0000 00x0 Graphics Enable Missle 1
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ENABL ds 1 ; $1F 0000 00x0 Graphics Enable Ball
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HMP0 ds 1 ; $20 xxxx 0000 Horizontal Motion Player 0
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HMP1 ds 1 ; $21 xxxx 0000 Horizontal Motion Player 1
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HMM0 ds 1 ; $22 xxxx 0000 Horizontal Motion Missle 0
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HMM1 ds 1 ; $23 xxxx 0000 Horizontal Motion Missle 1
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HMBL ds 1 ; $24 xxxx 0000 Horizontal Motion Ball
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VDELP0 ds 1 ; $25 0000 000x Vertical Delay Player 0
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VDELP1 ds 1 ; $26 0000 000x Vertical Delay Player 1
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VDELBL ds 1 ; $27 0000 000x Vertical Delay Ball
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RESMP0 ds 1 ; $28 0000 00x0 Reset Missle 0 to Player 0
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RESMP1 ds 1 ; $29 0000 00x0 Reset Missle 1 to Player 1
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HMOVE ds 1 ; $2A ---- ---- Apply Horizontal Motion
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HMCLR ds 1 ; $2B ---- ---- Clear Horizontal Move Registers
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CXCLR ds 1 ; $2C ---- ---- Clear Collision Latches
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;-------------------------------------------------------------------------------
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SEG.U TIA_REGISTERS_READ
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ORG TIA_BASE_READ_ADDRESS
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; bit 7 bit 6
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CXM0P ds 1 ; $00 xx00 0000 Read Collision M0-P1 M0-P0
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CXM1P ds 1 ; $01 xx00 0000 M1-P0 M1-P1
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CXP0FB ds 1 ; $02 xx00 0000 P0-PF P0-BL
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CXP1FB ds 1 ; $03 xx00 0000 P1-PF P1-BL
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CXM0FB ds 1 ; $04 xx00 0000 M0-PF M0-BL
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CXM1FB ds 1 ; $05 xx00 0000 M1-PF M1-BL
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CXBLPF ds 1 ; $06 x000 0000 BL-PF -----
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CXPPMM ds 1 ; $07 xx00 0000 P0-P1 M0-M1
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INPT0 ds 1 ; $08 x000 0000 Read Pot Port 0
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INPT1 ds 1 ; $09 x000 0000 Read Pot Port 1
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INPT2 ds 1 ; $0A x000 0000 Read Pot Port 2
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INPT3 ds 1 ; $0B x000 0000 Read Pot Port 3
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INPT4 ds 1 ; $0C x000 0000 Read Input (Trigger) 0
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INPT5 ds 1 ; $0D x000 0000 Read Input (Trigger) 1
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;-------------------------------------------------------------------------------
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SEG.U RIOT
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ORG $280
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; RIOT MEMORY MAP
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SWCHA ds 1 ; $280 Port A data register for joysticks:
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; Bits 4-7 for player 1. Bits 0-3 for player 2.
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SWACNT ds 1 ; $281 Port A data direction register (DDR)
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SWCHB ds 1 ; $282 Port B data (console switches)
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SWBCNT ds 1 ; $283 Port B DDR
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INTIM ds 1 ; $284 Timer output
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TIMINT ds 1 ; $285
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; Unused/undefined registers ($285-$294)
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ds 1 ; $286
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ds 1 ; $287
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ds 1 ; $288
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ds 1 ; $289
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ds 1 ; $28A
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ds 1 ; $28B
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ds 1 ; $28C
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ds 1 ; $28D
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ds 1 ; $28E
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ds 1 ; $28F
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ds 1 ; $290
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ds 1 ; $291
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ds 1 ; $292
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ds 1 ; $293
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TIM1T ds 1 ; $294 set 1 clock interval
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TIM8T ds 1 ; $295 set 8 clock interval
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TIM64T ds 1 ; $296 set 64 clock interval
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T1024T ds 1 ; $297 set 1024 clock interval
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;-------------------------------------------------------------------------------
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; The following required for back-compatibility with code which does not use
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; segments.
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SEG
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; EOF
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