1
0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-11-22 14:33:51 +00:00
8bitworkshop/test/cli/verilog/t_x_assign.v

17 lines
486 B
Coq
Raw Normal View History

// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2020 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t_x_assign(
input wire clk,
output reg o
);
always @(posedge clk) begin
if (1'bx) o <= 1'd1; else o <= 1'd0;
end
endmodule