mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-25 03:34:05 +00:00
287 lines
8.8 KiB
C
287 lines
8.8 KiB
C
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.setcpu "6502X"
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; TIA write registers
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VSYNC := $00 ; ---- --1- This address controls vertical sync time by writing D1 into the VSYNC latch.
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VBLANK := $01 ; 76-- --1- 1=Start VBLANK, 6=Enable INPT4, INPT5 latches, 7=Dump INPT1,2,3,6 to ground
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WSYNC := $02 ; ---- ---- This address halts microprocessor by clearing RDY latch to zero. RDY is set true again by the leading edge of horizontal blank.
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RSYNC := $03 ; ---- ---- This address resets the horizontal sync counter to define the beginning of horizontal blank time, and is used in chip testing.
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NUSIZ0 := $04 ; --54 -210 \ 0,1,2: player copys'n'size, 4,5: missile size: 2^x pixels
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NUSIZ1 := $05 ; --54 -210 /
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COLUP0 := $06 ; 7654 321- color player 0
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COLUP1 := $07 ; 7654 321- color player 1
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COLUPF := $08 ; 7654 321- color playfield
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COLUBK := $09 ; 7654 321- color background
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CTRLPF := $0A ; --54 -210 0=reflect playfield, 1=pf uses player colors, 2=playfield over sprites 4,5=ballsize:2^x
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REFP0 := $0B ; ---- 3--- reflect player 0
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REFP1 := $0C ; ---- 3--- reflect player 1
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PF0 := $0D ; DCBA ---- \ Playfield bits: ABCDEFGHIJKLMNOPQRST
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PF1 := $0E ; EFGH IJKL > normal: ABCDEFGHIJKLMNOPQRSTABCDEFGHIJKLMNOPQRST
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PF2 := $0F ; TSRQ PONM / reflect: ABCDEFGHIJKLMNOPQRSTTSRQPONMLKJIHGFEDCBA
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RESP0 := $10 ; ---- ---- \
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RESP1 := $11 ; ---- ---- \
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RESM0 := $12 ; ---- ---- > reset players, missiles and the ball. The object will begin its serial graphics at the time of a horizontal line at which the reset address occurs.
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RESM1 := $13 ; ---- ---- /
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RESBL := $14 ; ---- ---- /
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AUDC0 := $15 ; ---- 3210 audio control voice 0
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AUDC1 := $16 ; ---- 3210 audio control voice 1
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AUDF0 := $17 ; ---4 3210 frequency divider voice 0
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AUDF1 := $18 ; ---4 3210 frequency divider voice 1
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AUDV0 := $19 ; ---- 3210 audio volume voice 0
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AUDV1 := $1A ; ---- 3210 audio volume voice 1
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GRP0 := $1B ; 7654 3210 graphics player 0
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GRP1 := $1C ; 7654 3210 graphics player 1
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ENAM0 := $1D ; ---- --1- enable missile 0
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ENAM1 := $1E ; ---- --1- enable missile 1
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ENABL := $1F ; ---- --1- enable ball
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HMP0 := $20 ; 7654 ---- write data (horizontal motion values) into the horizontal motion registers
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HMP1 := $21 ; 7654 ---- write data (horizontal motion values) into the horizontal motion registers
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HMM0 := $22 ; 7654 ---- write data (horizontal motion values) into the horizontal motion registers
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HMM1 := $23 ; 7654 ---- write data (horizontal motion values) into the horizontal motion registers
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HMBL := $24 ; 7654 ---- write data (horizontal motion values) into the horizontal motion registers
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VDELP0 := $25 ; ---- ---0 delay player 0 by one vertical line
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VDELP1 := $26 ; ---- ---0 delay player 1 by one vertical line
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VDELBL := $27 ; ---- ---0 delay ball by one vertical line
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RESMP0 := $28 ; ---- --1- keep missile 0 aligned with player 0
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RESMP1 := $29 ; ---- --1- keep missile 1 aligned with player 1
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HMOVE := $2A ; ---- ---- This address causes the horizontal motion register values to be acted upon during the horizontal blank time in which it occurs.
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HMCLR := $2B ; ---- ---- This address clears all horizontal motion registers to zero (no motion).
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CXCLR := $2C ; ---- ---- clears all collision latches
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; TIA read registers
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CXM0P := $00 ; xx00 0000 Read Collision M0-P1 M0-P0
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CXM1P := $01 ; xx00 0000 M1-P0 M1-P1
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CXP0FB := $02 ; xx00 0000 P0-PF P0-BL
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CXP1FB := $03 ; xx00 0000 P1-PF P1-BL
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CXM0FB := $04 ; xx00 0000 M0-PF M0-BL
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CXM1FB := $05 ; xx00 0000 M1-PF M1-BL
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CXBLPF := $06 ; x000 0000 BL-PF -----
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CXPPMM := $07 ; xx00 0000 P0-P1 M0-M1
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INPT0 := $08 ; x000 0000 Read Pot Port 0
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INPT1 := $09 ; x000 0000 Read Pot Port 1
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INPT2 := $0A ; x000 0000 Read Pot Port 2
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INPT3 := $0B ; x000 0000 Read Pot Port 3
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INPT4 := $0C ; x000 0000 Read Input (Trigger) 0
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INPT5 := $0D ; x000 0000 Read Input (Trigger) 1
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; RIOT
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SWCHA := $0280
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SWACNT := $0281
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SWCHB := $0282
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SWBCNT := $0283
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INTIM := $0284 ; Timer output
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TIMINT := $0285
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TIM1T := $0294
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TIM8T := $0295
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TIM64T := $0296
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TIM1024T := $0297
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;-------------------------------------------------------------------------------
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; SLEEP duration
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; Original author: Thomas Jentzsch
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; Inserts code which takes the specified number of cycles to execute. This is
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; useful for code where precise timing is required.
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; ILLEGAL-OPCODE VERSION DOES NOT AFFECT FLAGS OR REGISTERS.
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; LEGAL OPCODE VERSION MAY AFFECT FLAGS
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; Uses illegal opcode (DASM 2.20.01 onwards).
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.macro SLEEP cycles
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.if cycles < 0 || cycles = 1
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.error "MACRO ERROR: 'SLEEP': Duration must be >= 2"
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.endif
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.if cycles & 1
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.ifndef NO_ILLEGAL_OPCODES
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nop 0
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.else
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bit VSYNC
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.endif
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.repeat (cycles-3)/2
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nop
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.endrep
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.else
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.repeat cycles/2
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nop
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.endrep
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.endif
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.endmacro
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;-------------------------------------------------------------------------------
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; VERTICAL_SYNC
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; revised version by Edwin Blink -- saves bytes!
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; Inserts the code required for a proper 3 scanline vertical sync sequence
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; Note: Alters the accumulator
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; OUT: A = 0
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.macro VERTICAL_SYNC
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lda #%1110 ; each '1' bits generate a VSYNC ON line (bits 1..3)
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: sta WSYNC ; 1st '0' bit resets Vsync, 2nd '0' bit exit loop
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sta VSYNC
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.ifdef VERTICAL_SYNC_MACRO
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pha
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VERTICAL_SYNC_MACRO
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pla
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.endif
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lsr
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bne :- ; branch until VYSNC has been reset
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.endmacro
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;-------------------------------------------------------
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; Usage: TIMER_SETUP lines
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; where lines is the number of scanlines to skip (> 2).
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; The timer will be set so that it expires before this number
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; of scanlines. A WSYNC will be done first.
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.macro TIMER_SETUP lines
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.local cycles
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cycles = ((lines * 76) - 13)
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; special case for when we have two timer events in a line
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; and our 2nd event straddles the WSYNC boundary
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.if (cycles .mod 64) < 12
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lda #(cycles / 64) - 1
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sta WSYNC
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.else
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lda #(cycles / 64)
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sta WSYNC
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.endif
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sta TIM64T
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.endmacro
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;-------------------------------------------------------
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; Use with TIMER_SETUP to wait for timer to complete.
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; Performs a WSYNC afterwards.
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.macro TIMER_WAIT
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.local waittimer
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waittimer:
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lda INTIM
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bne waittimer
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sta WSYNC
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.endmacro
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;-------------------------------------------------------------------------------
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; CLEAN_START
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; Original author: Andrew Davie
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; Standardised start-up code, clears stack, all TIA registers and RAM to 0
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; Sets stack pointer to $FF, and all registers to 0
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; Sets decimal mode off, sets interrupt flag (kind of un-necessary)
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; Use as very first section of code on boot (ie: at reset)
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; Code written to minimise total ROM usage - uses weird 6502 knowledge :)
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.macro CLEAN_START
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.local CLEAR_STACK
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sei
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cld
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ldx #0
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txa
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tay
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CLEAR_STACK: dex
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txs
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pha
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bne CLEAR_STACK ; SP=$FF, X = A = Y = 0
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.endmacro
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;-------------------------------------------------------
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; SET_POINTER
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; Original author: Manuel Rotschkar
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;
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; Sets a 2 byte RAM pointer to an absolute address.
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;
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; Usage: SET_POINTER pointer, address
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; Example: SET_POINTER SpritePTR, SpriteData
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;
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; Note: Alters the accumulator, NZ flags
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; IN 1: 2 byte RAM location reserved for pointer
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; IN 2: absolute address
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.macro SET_POINTER ptr, addr
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lda #<addr
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sta ptr
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lda #>addr
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sta ptr+1
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.endmacro
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; assume NTSC unless PAL defined
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.ifndef PAL
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PAL = 0
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.endif
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; 192 visible scanlines for NTSC, 228 for PAL
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.if PAL
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SCANLINES = 228
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LINESD12 = 19
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.else
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SCANLINES = 192
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LINESD12 = 16
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.endif
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; start of frame -- vsync and set back porch timer
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.macro FRAME_START
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VERTICAL_SYNC
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.if PAL
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TIMER_SETUP 44
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.else
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TIMER_SETUP 36
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.endif
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.endmacro
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; end of back porch -- start kernel
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.macro KERNEL_START
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TIMER_WAIT
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lda #0
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sta VBLANK
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.if !PAL
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TIMER_SETUP 194
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.endif
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.endmacro
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; end of kernel -- start front porch timer
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.macro KERNEL_END
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.if !PAL
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TIMER_WAIT
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.endif
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lda #2
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sta VBLANK
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.if PAL
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TIMER_SETUP 36
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.else
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TIMER_SETUP 28
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.endif
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.endmacro
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; end of frame -- jump to frame start
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.macro FRAME_END
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TIMER_WAIT
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.endmacro
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;-----------------------------------------------------------
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; SLEEPR - sleep macro that uses JSR/RTS for 12 cycle delays
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; Requires a lone RTS instruction with the label "Return"
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; (note: may fool 8bitworkshop's Anaylze CPU Timing feature)
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.macro SLEEPR cycles
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.if cycles >= 14 || cycles = 12
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jsr Return
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SLEEPR (cycles-12)
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.else
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SLEEP cycles
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.endif
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.endmacro
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;-----------------------------------------------------------
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; SLEEPH - sleep macro that uses PHA/PLA for 12 cycle delays
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.macro SLEEPH cycles
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.if cycles >= 9 || cycles = 7
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pha
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pla
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SLEEPH (cycles-7)
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.else
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SLEEP cycles
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.endif
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.endmacro
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