From 0ee201b9e82f08d632bc4458ed8161f8b3b218e7 Mon Sep 17 00:00:00 2001
From: Steven Hugg <hugg@fasterlight.com>
Date: Fri, 1 Jun 2018 10:33:37 -0700
Subject: [PATCH] update presets; redir.html expire

---
 presets/verilog/ball_absolute.v            | 10 ++--
 presets/verilog/ram.v                      | 16 +++---
 presets/verilog/ram1.v                     | 24 +--------
 presets/verilog/sprite_scanline_renderer.v | 60 +++++++++++++---------
 redir.html                                 | 13 +++++
 src/platform/verilog.js                    |  1 +
 6 files changed, 65 insertions(+), 59 deletions(-)

diff --git a/presets/verilog/ball_absolute.v b/presets/verilog/ball_absolute.v
index 634a62db..0de14ae6 100644
--- a/presets/verilog/ball_absolute.v
+++ b/presets/verilog/ball_absolute.v
@@ -18,7 +18,7 @@ module ball_absolute_top(clk, reset, hsync, vsync, rgb);
   reg [8:0] ball_vert_initial = 128;
   reg [8:0] ball_vert_move = 2;
   
-  localparam BALL_SIZE = 8;
+  localparam BALL_SIZE = 4;
   
   hvsync_generator hvsync_gen(
     .clk(clk),
@@ -54,16 +54,16 @@ module ball_absolute_top(clk, reset, hsync, vsync, rgb);
     ball_horiz_move <= -ball_horiz_move;
   end
   
-  wire [8:0] ball_hdiff = ball_hpos - hpos;
-  wire [8:0] ball_vdiff = ball_vpos - vpos;
+  wire [8:0] ball_hdiff = hpos - ball_hpos;
+  wire [8:0] ball_vdiff = vpos - ball_vpos;
 
   wire ball_hgfx = ball_hdiff < BALL_SIZE;
   wire ball_vgfx = ball_vdiff < BALL_SIZE;
   wire ball_gfx = ball_hgfx && ball_vgfx;
 
   // collide with vertical and horizontal boundaries
-  wire ball_vert_collide = ball_vgfx && (vpos==V_DISPLAY || vpos==0);
-  wire ball_horiz_collide = ball_hgfx && vpos==0 && (hpos==H_DISPLAY || hpos==0);
+  wire ball_vert_collide = ball_vpos >= 240 - BALL_SIZE;
+  wire ball_horiz_collide = ball_hpos >= 256 - BALL_SIZE;
   
   wire grid_gfx = (((hpos&7)==0) && ((vpos&7)==0));
 
diff --git a/presets/verilog/ram.v b/presets/verilog/ram.v
index d069fe66..667aee00 100644
--- a/presets/verilog/ram.v
+++ b/presets/verilog/ram.v
@@ -9,12 +9,12 @@ module RAM_sync(clk, addr, din, dout, we);
   parameter D = 8;  // # of data bits
   
   input  clk;		// clock
-  input  [A-1:0] addr;	// 10-bit address
-  input  [D-1:0] din;	// 8-bit data input
-  output [D-1:0] dout;	// 8-bit data output
+  input  [A-1:0] addr;	// address
+  input  [D-1:0] din;	// data input
+  output [D-1:0] dout;	// data output
   input  we;		// write enable
   
-  reg [D-1:0] mem [0:(1<<A)-1]; // 1024x8 bit memory
+  reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
   
   always @(posedge clk) begin
     if (we)		// if write enabled
@@ -30,12 +30,12 @@ module RAM_async(clk, addr, din, dout, we);
   parameter D = 8;  // # of data bits
   
   input  clk;		// clock
-  input  [A-1:0] addr;	// 10-bit address
-  input  [D-1:0] din;	// 8-bit data input
-  output [D-1:0] dout;	// 8-bit data output
+  input  [A-1:0] addr;	// address
+  input  [D-1:0] din;	// data input
+  output [D-1:0] dout;	// data output
   input  we;		// write enable
   
-  reg [D-1:0] mem [0:(1<<A)-1]; // 1024x8 bit memory
+  reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
   
   always @(posedge clk) begin
     if (we)		// if write enabled
diff --git a/presets/verilog/ram1.v b/presets/verilog/ram1.v
index e727e775..1c9e1435 100644
--- a/presets/verilog/ram1.v
+++ b/presets/verilog/ram1.v
@@ -1,26 +1,6 @@
 `include "hvsync_generator.v"
 `include "digits10.v"
-
-module RAM(clk, addr, din, dout, we);
-  
-  parameter A = 10; // # of address bits
-  parameter D = 8;  // # of data bits
-  
-  input  clk;		// clock
-  input  [A-1:0] addr;	// 10-bit address
-  input  [D-1:0] din;	// 8-bit data input
-  output [D-1:0] dout;	// 8-bit data output
-  input  we;		// write enable
-  
-  reg [D-1:0] mem [0:(1<<A)-1]; // 1024x8 bit memory
-  
-  always @(posedge clk) begin
-    if (we)		// if write enabled
-      mem[addr] <= din;	// write memory from din
-    dout <= mem[addr];	// read memory to dout
-  end
-
-endmodule
+`include "ram.v"
 
 module test_ram1_top(clk, reset, hsync, vsync, rgb);
 
@@ -38,7 +18,7 @@ module test_ram1_top(clk, reset, hsync, vsync, rgb);
   reg ram_writeenable = 0;
   
   // RAM to hold 32x32 array of bytes
-  RAM ram(
+  RAM_sync ram(
     .clk(clk),
     .dout(ram_read),
     .din(ram_write),
diff --git a/presets/verilog/sprite_scanline_renderer.v b/presets/verilog/sprite_scanline_renderer.v
index bb357f42..5dedc559 100644
--- a/presets/verilog/sprite_scanline_renderer.v
+++ b/presets/verilog/sprite_scanline_renderer.v
@@ -35,44 +35,54 @@ module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
                                ram_addr, ram_data, ram_busy,
                                rom_addr, rom_data);
 
-  parameter NB = 5;
-  parameter MB = 3;
+  parameter NB = 5; // 2^NB == number of sprites
+  parameter MB = 3; // 2^MB == slots per scanline
   
-  localparam N = 1<<NB;
-  localparam M = 1<<MB;
+  localparam N = 1<<NB; // number of sprites
+  localparam M = 1<<MB; // slots per scanline
   
   input clk, reset;
   input [8:0] hpos;
   input [8:0] vpos;
   output [3:0] rgb;
 
-  output [NB:0] ram_addr;
-  input [15:0] ram_data;
-  output ram_busy;
+  output [NB:0] ram_addr; // RAM for sprite data
+  input [15:0] ram_data;  // (2 words per sprite)
+  output ram_busy;	  // set when accessing RAM
   
-  output [15:0] rom_addr;
-  input [15:0] rom_data;
+  output [15:0] rom_addr; // sprite ROM address
+  input [15:0] rom_data;  // sprite ROM data
   
+  // copy of sprite data from RAM
   reg [7:0] sprite_xpos[0:N-1];
   reg [7:0] sprite_ypos[0:N-1];
   reg [7:0] sprite_attr[0:N-1];
   
+  // mapping of N sprites to M line slots
   reg [NB-1:0] sprite_to_line[0:M-1];
-  reg [7:0] line_xpos[0:M-1];
-  reg [7:0] line_yofs[0:M-1];
-  reg [7:0] line_attr[0:M-1];
-  reg line_active[0:M-1];
-  reg [3:0] scanline[0:511];
+
+  reg [7:0] line_xpos[0:M-1]; // X pos for M slots
+  reg [7:0] line_yofs[0:M-1]; // Y pos for M slots
+  reg [7:0] line_attr[0:M-1]; // attr for M slots
+  reg line_active[0:M-1];     // slot active?
+  
+  // temporary counters
   reg [NB-1:0] i; // 0..N-1
   reg [MB-1:0] j; // 0..M-1
   reg [MB-1:0] k; // 0..M-1
   reg [7:0] z;
   reg [8:0] write_ofs;
-  
-  wire [8:0] read_bufidx = {vpos[0], hpos[7:0]};
   reg [15:0] out_bitmap;
   reg [7:0] out_attr;
-  wire [NB-1:0] load_index = hpos[NB+2:3];
+
+  // which sprite are we currently reading?
+  wire [NB-1:0] load_index = hpos[NB+1:2];
+
+  // RGB dual scanline buffer
+  reg [3:0] scanline[0:511];  
+  
+  // which offset in scanline buffer to read?
+  wire [8:0] read_bufidx = {vpos[0], hpos[7:0]};
   
   /*
   0: read sprite_ypos[i]
@@ -95,18 +105,20 @@ module sprite_scanline_renderer(clk, reset, hpos, vpos, rgb,
       // load sprites from RAM on line 260
       // 8 cycles per sprite
       // do first sprite twice b/c CPU might still be busy
-      if (vpos == 260 && hpos < N*8+8) begin
+      if (vpos == 260 && hpos < N*4+8) begin
         ram_busy <= 1;
-        case (hpos[2:0])
-          3: begin
+        case (hpos[1:0])
+          0: begin
             ram_addr <= {load_index, 1'b0};
           end
-          5: begin
-            sprite_xpos[load_index] <= ram_data[7:0];
-            sprite_ypos[load_index] <= ram_data[15:8];
+          1: begin
             ram_addr <= {load_index, 1'b1};
           end
-          7: begin
+          2: begin
+            sprite_xpos[load_index] <= ram_data[7:0];
+            sprite_ypos[load_index] <= ram_data[15:8];
+          end
+          3: begin
             sprite_attr[load_index] <= ram_data[7:0];
           end
         endcase
diff --git a/redir.html b/redir.html
index 287e1701..da9ecdfe 100644
--- a/redir.html
+++ b/redir.html
@@ -1,4 +1,17 @@
+<html>
+
+<head>
+<meta http-equiv="Cache-Control" content="no-cache, no-store, must-revalidate" />
+<meta http-equiv="Pragma" content="no-cache" />
+<meta http-equiv="Expires" content="0" />
+</head>
+
 <script>
 var VERSION = '2.1.1';
 document.location.href = 'v' + VERSION + '/' + document.location.search;
 </script>
+
+<body>
+</body>
+
+</html>
diff --git a/src/platform/verilog.js b/src/platform/verilog.js
index ff87e4ac..09977943 100644
--- a/src/platform/verilog.js
+++ b/src/platform/verilog.js
@@ -7,6 +7,7 @@ var VERILOG_PRESETS = [
   {id:'7segment.v', name:'7-Segment Decoder'},
   {id:'digits10.v', name:'Bitmapped Digits'},
   {id:'scoreboard.v', name:'Scoreboard'},
+  {id:'ball_absolute.v', name:'Ball Motion (absolute position)'},
   {id:'ball_slip_counter.v', name:'Ball Motion (slipping counter)'},
   {id:'ball_paddle.v', name:'Brick Smash Game'},
   {id:'ram1.v', name:'RAM Text Display'},