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CYCLES_PER_FILL

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This commit is contained in:
Steven Hugg 2020-09-16 22:12:21 -05:00
parent 6134f90b13
commit 11bdd3cf63
2 changed files with 6 additions and 4 deletions
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6
package-lock.json generated
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@ -2967,9 +2967,9 @@
}
},
"node-fetch": {
"version": "2.6.0",
"resolved": "https://registry.npmjs.org/node-fetch/-/node-fetch-2.6.0.tgz",
"integrity": "sha512-8dG4H5ujfvFiqDmVu9fQ5bOHUC15JMjMY/Zumv26oOvvVJjM67KF8koCWIabKQ1GJIa9r2mMZscBq/TbdOcmNA==",
"version": "2.6.1",
"resolved": "https://registry.npmjs.org/node-fetch/-/node-fetch-2.6.1.tgz",
"integrity": "sha512-V4aYg89jEoVRxRb2fJdAg8FHvI7cEyYdVAh94HH0UIK8oJxUfkjlDQN9RbMx+bEjP7+ggMiFRprSti032Oipxw==",
"dev": true
},
"normalize-package-data": {

4
src/platform/verilog.ts
View File

@ -159,6 +159,8 @@ export function VL_READMEM_W(ishex,width,depth,array_lsb,fnwords,filename,memp,s
memp[i] = data[i];
}
const CYCLES_PER_FILL = 20;
// SIMULATOR BASE
abstract class VerilatorBase {
@ -483,7 +485,7 @@ var VerilogPlatform = function(mainElement, options) {
updateScopeFrame() {
this.split.setSizes([0,100]); // ensure scope visible
//this.topdiv.hide();// hide crt
var done = this.fillTraceBuffer(32 * trace_signals.length); // TODO: const
var done = this.fillTraceBuffer(CYCLES_PER_FILL * trace_signals.length);
if (done)
this.pause(); // TODO?
// TODO