6502/8bitworkshop
1
0
Fork 0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-11-28 23:49:20 +00:00
Code Issues Projects Releases Wiki Activity

make sure inspect var is not array

Browse Source
This commit is contained in:
Steven Hugg 2018-03-18 20:11:11 -05:00
parent f24213aa1d
commit 1b3822050a
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
presets/verilog/femto16.json
View File

@ -1,5 +1,5 @@
{ {
"name":"femto8", "name":"femto16",
"width":16, "width":16,
"vars":{ "vars":{
"reg":{"bits":3, "toks":["ax", "bx", "cx", "dx", "ex", "fx", "sp", "ip"]}, "reg":{"bits":3, "toks":["ax", "bx", "cx", "dx", "ex", "fx", "sp", "ip"]},
@ -25,6 +25,8 @@
{"fmt":"pop ~reg", "bits":["01001",0,"00001","110"]}, {"fmt":"pop ~reg", "bits":["01001",0,"00001","110"]},
{"fmt":"rts", "bits":["01001","111","00001","110"]}, {"fmt":"rts", "bits":["01001","111","00001","110"]},
{"fmt":"jsr ~reg", "bits":["01110","111","00",0,"110"]}, {"fmt":"jsr ~reg", "bits":["01110","111","00",0,"110"]},
{"fmt":"jsrex ~imm16", "bits":["0001110001011000",0,"0111011100100110"]},
{"fmt":"jmp ~imm16", "bits":["0001111101011000",0]},
{"fmt":"bcc ~rel8", "bits":["10000001",0]}, {"fmt":"bcc ~rel8", "bits":["10000001",0]},
{"fmt":"bcs ~rel8", "bits":["10001001",0]}, {"fmt":"bcs ~rel8", "bits":["10001001",0]},

2
src/platform/verilog.js
View File

@ -697,7 +697,7 @@ var VerilogPlatform = function(mainElement, options) {
val = gen[name]; val = gen[name];
} }
} }
if (val !== undefined) { if (typeof(val) === 'number') {
inspect_obj = gen; inspect_obj = gen;
inspect_sym = name; inspect_sym = name;
} else { } else {