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verilog: support /

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Steven Hugg 2019-09-07 20:00:48 -04:00
parent 894ac96be3
commit 1d5d2cddf0
1 changed files with 3 additions and 0 deletions
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src/platform/verilog.ts
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@ -94,6 +94,9 @@ export function VL_LTES_III(x,lbits,y,lhs,rhs) {
export function VL_GTES_III(x,lbits,y,lhs,rhs) {
return (VL_EXTENDS_II(x,lbits,lhs) >= VL_EXTENDS_II(x,lbits,rhs)) ? 1 : 0; }
export function VL_DIV_III(lbits,lhs,rhs) {
return (((rhs)==0)?0:(lhs)/(rhs)); }
export function VL_MODDIV_III(lbits,lhs,rhs) {
return (((rhs)==0)?0:(lhs)%(rhs)); }