From 2fce80bc9d9dd485aab952ddffd9d5c7cdb6df5e Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Sat, 14 Jul 2018 23:29:27 -0500 Subject: [PATCH] fixed asmlines in inline asm; reset h/vpaddle on vsync; fixed framebuffer.v --- doc/notes.txt | 1 + presets/verilog/framebuffer.v | 7 +++---- presets/verilog/lfsr.v | 4 ++-- presets/verilog/racing_game_cpu.v | 8 ++++---- presets/verilog/test2.asm | 2 +- src/platform/verilog.js | 3 +++ src/worker/workermain.js | 2 +- 7 files changed, 15 insertions(+), 12 deletions(-) diff --git a/doc/notes.txt b/doc/notes.txt index ee2c785e..b938177d 100644 --- a/doc/notes.txt +++ b/doc/notes.txt @@ -47,6 +47,7 @@ TODO: - verilog debugging makes it slow - fix VCS mame - remove FPS and play controls when Verilog scope paused +- compile stuck when errors unchanged WEB WORKER FORMAT diff --git a/presets/verilog/framebuffer.v b/presets/verilog/framebuffer.v index 31d97527..17b8a422 100644 --- a/presets/verilog/framebuffer.v +++ b/presets/verilog/framebuffer.v @@ -1,5 +1,4 @@ `include "hvsync_generator.v" -`include "cpu8.v" `include "cpu16.v" // uncomment to see scope view @@ -85,9 +84,9 @@ module frame_buffer_top(clk, reset, hsync, vsync, hpaddle, vpaddle, reg hold; wire busy; reg [15:0] vline[0:31]; // 32x16 bits = 256 4-color pixels - reg [4:0] vindex; - reg [15:0] vshift; - reg [3:0] palette[0:3] = '{0,1,4,7}; + reg [4:0] vindex; // index into line array + reg [15:0] vshift; // shift register with current word to output + reg [3:0] palette[0:3] = '{0,1,4,7}; // simple palette always @(posedge clk) begin // has CPU released the bus? diff --git a/presets/verilog/lfsr.v b/presets/verilog/lfsr.v index bd551d2f..440cacde 100644 --- a/presets/verilog/lfsr.v +++ b/presets/verilog/lfsr.v @@ -15,8 +15,8 @@ module LFSR(clk,reset,enable,lfsr); always @(posedge clk) begin - if (reset) // initialize to 1 - lfsr <= {lfsr[NBITS-2:1], 1'b0, 1'b1}; + if (reset) + lfsr <= {lfsr[NBITS-2:0], ~lfsr[0]}; else if (enable) lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0); end diff --git a/presets/verilog/racing_game_cpu.v b/presets/verilog/racing_game_cpu.v index 0acd966f..04de9427 100644 --- a/presets/verilog/racing_game_cpu.v +++ b/presets/verilog/racing_game_cpu.v @@ -47,9 +47,9 @@ module racing_game_cpu_top(clk, reset, hsync, vsync, hpaddle, vpaddle, parameter TRACKPOS_LO = 8; parameter TRACKPOS_HI = 9; - parameter IN_HPOS = 8'b01000000; - parameter IN_VPOS = 8'b01000001; - parameter IN_FLAGS = 8'b01000010; + parameter IN_HPOS = 8'h40; + parameter IN_VPOS = 8'h41; + parameter IN_FLAGS = 8'h42; reg [7:0] ram[0:63]; reg [7:0] rom[0:127]; @@ -81,7 +81,7 @@ module racing_game_cpu_top(clk, reset, hsync, vsync, hpaddle, vpaddle, vsync, hsync, vpaddle, hpaddle, display_on}; // ROM 8'b1???????: to_cpu = rom[address_bus[6:0]]; - default: ; + default: to_cpu = 8'bxxxxxxxx; endcase hvsync_generator hvsync_gen( diff --git a/presets/verilog/test2.asm b/presets/verilog/test2.asm index e19b3cbd..b7224061 100644 --- a/presets/verilog/test2.asm +++ b/presets/verilog/test2.asm @@ -12,7 +12,7 @@ .arch femto16 .org 0x8000 -.len 1024 +.len 32768 .define ScreenBuffer $6000 .define PageTable $7e00 diff --git a/src/platform/verilog.js b/src/platform/verilog.js index 6f7f9a41..5674c6c9 100644 --- a/src/platform/verilog.js +++ b/src/platform/verilog.js @@ -318,6 +318,8 @@ var VerilogPlatform = function(mainElement, options) { framey = 0; framex = 0; frameidx = 0; + gen.hpaddle = 0; + gen.vpaddle = 0; } else { var wasvsync = framevsync; framevsync = false; @@ -524,6 +526,7 @@ var VerilogPlatform = function(mainElement, options) { ctx.fillStyle = "white"; ctx.textAlign = "left"; setKeyboardFromMap(video, switches, VERILOG_KEYCODE_MAP); + // TODO: make it stop incrementing time when clicked $(video.canvas).mousemove(function(e) { var new_x = Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width() - 20); var new_y = Math.floor(e.offsetY * video.canvas.height / $(video.canvas).height() - 20); diff --git a/src/worker/workermain.js b/src/worker/workermain.js index 91c63909..09ed438d 100644 --- a/src/worker/workermain.js +++ b/src/worker/workermain.js @@ -1204,7 +1204,7 @@ function compileVerilator(step) { rtn.listings = {}; // TODO: what if found in non-top-module? if (asmlines.length) - rtn.listings[topmod+'.v'] = {lines:asmlines}; + rtn.listings[step.path] = {lines:asmlines}; return rtn; } catch(e) { console.log(e);