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verilog: working on 64-bit, debug tree, fix 1-bit sound

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This commit is contained in:
Steven Hugg
2021-07-04 12:00:25 -05:00
parent 854a6a2cdc
commit 3ec69792b0
6 changed files with 255 additions and 95 deletions
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test/cli/testverilog.js
+31 -13
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@@ -1,7 +1,10 @@
var assert = require('assert');
var _path = require('path')
var _cproc = require('child_process');
var fs = require('fs');
var wtu = require('./workertestutils.js');
createTestDOM();
var emu = require('gen/common/emu.js');
@@ -61,7 +64,7 @@ function testPerf(msg) {
return platform;
}
function compileVerilator(filename, code, callback, nerrors) {
function compileVerilator(filename, code, callback, nerrors, depends) {
global.postMessage = async function(msg) {
if (msg.errors && msg.errors.length) {
console.log(msg.errors);
@@ -77,26 +80,43 @@ function compileVerilator(filename, code, callback, nerrors) {
callback(null, msg);
};
global.onmessage({
data:{code:code, platform:'verilog', tool:'verilator', path:'main.v'}
data:{
updates:[{path:_path.basename(filename), data:code}],
buildsteps:[{path:_path.basename(filename), platform:'verilog', tool:'verilator', files:depends}]
}
});
}
function testVerilator(filename, disables, nerrors) {
function testIcarus(filename) {
_cproc.execSync('iverilog -I./presets/verilog ./' + filename);
}
function testVerilator(filename, disables, nerrors, depends) {
it('should translate '+filename, function(done) {
console.log(filename);
//if (depends) testIcarus(filename);
var csource = ab2str(fs.readFileSync(filename));
for (var i=0; i<(disables||[]).length; i++)
csource = "/* verilator lint_off " + disables[i] + " */\n" + csource;
compileVerilator(filename, csource, done, nerrors||0);
csource = "/* verilator lint_off " + disables[i] + " */ " + csource;
compileVerilator(filename, csource, done, nerrors||0, depends);
});
}
describe('Verilog Worker', function() {
testVerilator('presets/verilog/hvsync_generator.v');
testVerilator('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/ball_paddle.v', null, null, ['ball_paddle.v', 'scoreboard.v', 'digits10.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/sprite_rotation.v', null, null, ['sprite_rotation.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/lfsr.v');
testVerilator('presets/verilog/starfield.v', null, null, ['starfield.v', 'lfsr.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/ram.v');
// TODO: how to include files?
testVerilator('presets/verilog/font_cp437_8x8.v');
testVerilator('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']);
testVerilator('presets/verilog/cpu6502.v');
// TODO: how to include files? have to pass buildsteps + files
//testVerilator('test/cli/verilog/t_tri_gate.v');
testVerilator('test/cli/verilog/t_tri_gen.v', ['UNDRIVEN']);
@@ -109,13 +129,13 @@ describe('Verilog Worker', function() {
testVerilator('test/cli/verilog/t_tri_unconn.v', ['PINCONNECTEMPTY']);
testVerilator('test/cli/verilog/t_tri_various.v', ['UNDRIVEN']);
/* TODO: fix tests
testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_alw_combdly.v');
testVerilator('test/cli/verilog/t_math_const.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_alw_combdly.v');
testVerilator('test/cli/verilog/t_clk_first.v', ['UNDRIVEN','SYNCASYNCNET']);
/* TODO: fix tests
testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_clk_2in.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_order_comboclkloop.v');
*/
testVerilator('test/cli/verilog/t_gen_alw.v');
@@ -144,7 +164,7 @@ describe('Verilog Worker', function() {
testVerilator('test/cli/verilog/t_math_arith.v', ['BLKSEQ']);
//testVerilator('test/cli/verilog/t_math_div.v');
testVerilator('test/cli/verilog/t_math_div0.v');
//testVerilator('test/cli/verilog/t_math_div0.v');
testVerilator('test/cli/verilog/t_clk_powerdn.v', ['BLKSEQ','SYNCASYNCNET']);
//testVerilator('test/cli/verilog/t_clk_latchgate.v', ['BLKSEQ']);
@@ -155,8 +175,6 @@ describe('Verilog Worker', function() {
testVerilator('test/cli/verilog/t_clk_condflop_nord.v');
testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']);
testVerilator('presets/verilog/hvsync_generator.v');
testVerilator('presets/verilog/cpu6502.v');
/*
it('should compile verilog example', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v'));