From 42920337ecf1b0e2bdb7cb3b84c27bd209ca2b42 Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Thu, 8 Jul 2021 15:15:33 -0500 Subject: [PATCH] verilog: fix optimization for tick2(), removed > 64 bit tests, stop tracing when $stop/$finish, +SignExt --- src/common/hdl/hdlwasm.ts | 41 ++- src/platform/verilog.ts | 6 +- test/cli/testverilog.js | 28 +- test/cli/verilog/t_math_cmp.v | 169 ------------- test/cli/verilog/t_math_concat.v | 75 ------ test/cli/verilog/t_math_concat64.v | 131 ---------- test/cli/verilog/t_math_div.v | 115 --------- test/cli/verilog/t_math_equal.v | 74 ------ test/cli/verilog/t_math_msvc_64.v | 75 ------ test/cli/verilog/t_math_pick.v | 83 ------ test/cli/verilog/t_math_red.v | 65 ----- test/cli/verilog/t_math_repl.v | 110 -------- test/cli/verilog/t_math_shift.v | 239 ------------------ test/cli/verilog/t_math_shift_rep.v | 78 ------ test/cli/verilog/t_math_shiftrs.v | 57 ----- test/cli/verilog/t_math_vliw.v | 104 -------- test/cli/verilog/t_mem_fifo.v | 111 -------- test/cli/verilog/t_mem_multidim.v | 100 -------- test/cli/verilog/t_mem_packed.v | 180 ------------- .../verilog/t_no_sel_assign_merge_in_cpp.v | 14 - test/cli/verilog/t_order_comboloop.v | 57 ----- test/cli/verilog/t_param_array5.v | 39 --- test/cli/verilog/t_select_little.v | 75 ------ test/cli/verilog/t_unroll_forfor.v | 35 --- test/cli/verilog/t_var_assign_landr.v | 91 ------- test/cli/verilog/t_var_pinsizes.v | 68 ----- 26 files changed, 35 insertions(+), 2185 deletions(-) delete mode 100644 test/cli/verilog/t_math_cmp.v delete mode 100644 test/cli/verilog/t_math_concat.v delete mode 100644 test/cli/verilog/t_math_concat64.v delete mode 100644 test/cli/verilog/t_math_div.v delete mode 100644 test/cli/verilog/t_math_equal.v delete mode 100644 test/cli/verilog/t_math_msvc_64.v delete mode 100644 test/cli/verilog/t_math_pick.v delete mode 100644 test/cli/verilog/t_math_red.v delete mode 100644 test/cli/verilog/t_math_repl.v delete mode 100644 test/cli/verilog/t_math_shift.v delete mode 100644 test/cli/verilog/t_math_shift_rep.v delete mode 100644 test/cli/verilog/t_math_shiftrs.v delete mode 100644 test/cli/verilog/t_math_vliw.v delete mode 100644 test/cli/verilog/t_mem_fifo.v delete mode 100644 test/cli/verilog/t_mem_multidim.v delete mode 100644 test/cli/verilog/t_mem_packed.v delete mode 100644 test/cli/verilog/t_no_sel_assign_merge_in_cpp.v delete mode 100644 test/cli/verilog/t_order_comboloop.v delete mode 100644 test/cli/verilog/t_param_array5.v delete mode 100644 test/cli/verilog/t_select_little.v delete mode 100644 test/cli/verilog/t_unroll_forfor.v delete mode 100644 test/cli/verilog/t_var_assign_landr.v delete mode 100644 test/cli/verilog/t_var_pinsizes.v diff --git a/src/common/hdl/hdlwasm.ts b/src/common/hdl/hdlwasm.ts index a0fed167..1049d019 100644 --- a/src/common/hdl/hdlwasm.ts +++ b/src/common/hdl/hdlwasm.ts @@ -192,7 +192,8 @@ export class HDLModuleWASM implements HDLModuleRunner { traceEndOffset: number; trace: any; getFileData = null; - maxMemoryMB : number; + maxMemoryMB: number; + optimize: boolean = false; constructor(moddef: HDLModuleDef, constpool: HDLModuleDef, maxMemoryMB?: number) { this.hdlmod = moddef; @@ -308,6 +309,7 @@ export class HDLModuleWASM implements HDLModuleRunner { private genMemory() { this.bmod = new binaryen.Module(); + this.bmod.setFeatures(binaryen.Features.SignExt); this.genTypes(); var membytes = this.globals.len; if (membytes > this.maxMemoryMB*1024*1024) @@ -375,13 +377,20 @@ export class HDLModuleWASM implements HDLModuleRunner { } private validate() { - // validate wasm module - //console.log(this.bmod.emitText()); - //this.bmod.optimize(); - if (!this.bmod.validate()) { + // optimize wasm module (default passes crash binaryen.js) + if (this.optimize) { + var size = this.bmod.emitBinary().length; + // TODO: more passes? + // https://github.com/WebAssembly/binaryen/blob/369b8bdd3d9d49e4d9e0edf62e14881c14d9e352/src/passes/pass.cpp#L396 + this.bmod.runPasses(['dce','optimize-instructions','precompute','simplify-locals','simplify-globals','rse','vacuum'/*,'dae-optimizing','inlining-optimizing'*/]) + var optsize = this.bmod.emitBinary().length; + console.log('optimize', size, '->', optsize) + } + // validate wasm module + if (!this.bmod.validate()) { //console.log(this.bmod.emitText()); throw new HDLError(null, `could not validate wasm module`); - } + } } private genFunction(block) { @@ -602,23 +611,26 @@ export class HDLModuleWASM implements HDLModuleRunner { const m = this.bmod; var l_loop = this.label("@loop"); if (this.globals.lookup('clk')) { - var l_dseg = m.local.get(0, binaryen.i32); - var l_count = m.local.get(1, binaryen.i32); + var v_dseg = m.local.get(0, binaryen.i32); + //var v_count = m.local.get(1, binaryen.i32); m.addFunction("tick2", binaryen.createType([binaryen.i32, binaryen.i32]), binaryen.none, [], m.loop(l_loop, m.block(null, [ this.makeSetVariableFunction("clk", 0), - m.drop(m.call("eval", [l_dseg], binaryen.i32)), + m.drop(m.call("eval", [v_dseg], binaryen.i32)), this.makeSetVariableFunction("clk", 1), - m.drop(m.call("eval", [l_dseg], binaryen.i32)), + m.drop(m.call("eval", [v_dseg], binaryen.i32)), // call copyTraceRec m.call("copyTraceRec", [], binaryen.none), - // dec $1 - m.local.set(1, m.i32.sub(l_count, m.i32.const(1))), - // goto @loop if $1 - m.br_if(l_loop, l_count) + // goto @loop if ($1 = $1 - 1) + m.br_if(l_loop, + m.local.tee(1, + m.i32.sub( + m.local.get(1, binaryen.i32), + m.i32.const(1) + ), binaryen.i32)) ])) ); m.addFunctionExport("tick2", "tick2"); @@ -1014,6 +1026,7 @@ export class HDLModuleWASM implements HDLModuleRunner { return this.bmod.i64.extend32_s(value); } } + // TODO: this might not work? (t_math_signed2.v) var shift = inst.const(e.width - e.widthminv, 0); return inst.shr_s(inst.shl(value, shift), shift); } diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts index ab184d79..1fc3248a 100644 --- a/src/platform/verilog.ts +++ b/src/platform/verilog.ts @@ -508,7 +508,9 @@ var VerilogPlatform = function(mainElement, options) { fillTraceBuffer(count:number) : boolean { var max_index = Math.min(trace_buffer.length - trace_signals.length, trace_index + count); while (trace_index < max_index) { - top.tick(); + if (!top.isStopped() && !top.isFinished()) { + top.tick(); + } this.snapshotTrace(); if (trace_index == 0) break; @@ -778,7 +780,7 @@ var VerilogPlatform = function(mainElement, options) { }; } else if (top instanceof HDLModuleWASM) { return { - extension:".wasm", + extension:".wat", blob: new Blob([top.bmod.emitText()], {type:"text/plain"}) }; } diff --git a/test/cli/testverilog.js b/test/cli/testverilog.js index 4641bf52..2eb740ea 100644 --- a/test/cli/testverilog.js +++ b/test/cli/testverilog.js @@ -28,7 +28,7 @@ async function loadPlatform(msg) { //console.log(msg.output.ports); //console.log(msg.output.signals); await platform.loadROM("ROM", msg.output); - await platform.loadROM("ROM", msg.output); + //await platform.loadROM("ROM", msg.output); for (var i=0; i<100000 && !platform.isBlocked(); i++) { platform.tick(); } @@ -49,27 +49,6 @@ async function loadPlatform(msg) { return platform; } -function testPerf(msg) { - var platform = new VerilogPlatform(); - platform.loadROM("ROM", msg.output); - var niters = 5000000; - - console.time("before"); - for (var i=0; i3'd4) index_a=3'd4; - index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; - end - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module prover ( - input clk, - input [2:0] index_a, - input [2:0] index_b - ); - - parameter WIDTH = 4; - - - reg signed [WIDTH-1:0] as; - reg signed [WIDTH-1:0] bs; - wire [WIDTH-1:0] b = bs; - - // verilator lint_off LATCH - always @* begin - casez (index_a) - 3'd0: as = {(WIDTH){1'd0}}; // 0 - 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: as = {(WIDTH){1'd1}}; // -1 - 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; - endcase - casez (index_b) - 3'd0: bs = {(WIDTH){1'd0}}; // 0 - 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: bs = {(WIDTH){1'd1}}; // -1 - 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; - endcase - end - // verilator lint_on LATCH - - reg [7:0] results[4:0][4:0]; - - wire gt = as>b; - wire gts = as>bs; - wire gte = as>=b; - wire gtes = as>=bs; - wire lt = as2) begin -`ifdef TEST_VERBOSE - $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", - index_a, index_b, - gt, gts, gte, gtes, lt, lts, lte, ltes); -`endif - exp = results[index_a][index_b]; - got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; - if (exp !== got) begin - $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); - $stop; - end - end - end - - // Result table - initial begin - // Indexes: 0, 1, -1, 127, -128 - // Gt Gts Gte Gtes Lt Lts Lte Ltes - results[0][0] = 8'b0_0_1_1_0_0_1_1; - results[0][1] = 8'b0_0_0_0_1_1_1_1; - results[0][2] = 8'b0_0_1_1_0_0_1_1; - results[0][3] = 8'b0_1_0_1_1_0_1_0; - results[0][4] = 8'b0_1_0_1_1_0_1_0; - results[1][0] = 8'b1_1_1_1_0_0_0_0; - results[1][1] = 8'b0_0_1_1_0_0_1_1; - results[1][2] = 8'b1_1_1_1_0_0_0_0; - results[1][3] = 8'b0_1_0_1_1_0_1_0; - results[1][4] = 8'b0_1_0_1_1_0_1_0; - results[2][0] = 8'b0_0_1_1_0_0_1_1; - results[2][1] = 8'b0_0_0_0_1_1_1_1; - results[2][2] = 8'b0_0_1_1_0_0_1_1; - results[2][3] = 8'b0_1_0_1_1_0_1_0; - results[2][4] = 8'b0_1_0_1_1_0_1_0; - results[3][0] = 8'b1_0_1_0_0_1_0_1; - results[3][1] = 8'b1_0_1_0_0_1_0_1; - results[3][2] = 8'b1_0_1_0_0_1_0_1; - results[3][3] = 8'b0_0_1_1_0_0_1_1; - results[3][4] = 8'b1_1_1_1_0_0_0_0; - results[4][0] = 8'b1_0_1_0_0_1_0_1; - results[4][1] = 8'b1_0_1_0_0_1_0_1; - results[4][2] = 8'b1_0_1_0_0_1_0_1; - results[4][3] = 8'b0_0_0_0_1_1_1_1; - results[4][4] = 8'b0_0_1_1_0_0_1_1; - end - -endmodule diff --git a/test/cli/verilog/t_math_concat.v b/test/cli/verilog/t_math_concat.v deleted file mode 100644 index a70ec1af..00000000 --- a/test/cli/verilog/t_math_concat.v +++ /dev/null @@ -1,75 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [255:0] i; - wire [255:0] q; - - assign q = { - i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], - i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], - i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], - i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], - i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], - i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], - i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], - i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], - i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], - i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], - i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], - i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], - i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], - i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], - i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], - i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], - i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], - i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], - i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], - i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], - i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], - i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], - i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], - i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], - i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], - i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], - i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], - i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], - i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], - i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], - i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], - i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] - }; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; -`ifdef TEST_VERBOSE - $write("%x %x\n", q, i); -`endif - if (cyc==1) begin - i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - end - if (cyc==2) begin - i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; - end - if (cyc==3) begin - if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_concat64.v b/test/cli/verilog/t_math_concat64.v deleted file mode 100644 index 54f1ec60..00000000 --- a/test/cli/verilog/t_math_concat64.v +++ /dev/null @@ -1,131 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [127:0] i; - wire [127:0] q1; - wire [127:0] q32; - wire [127:0] q64; - wire [63:0] q64_low; - - assign q1 = { - i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], - i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], - i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], - i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], - - i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], - i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], - i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], - i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1], - - i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], - i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], - i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], - i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], - - i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], - i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], - i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], - i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - - assign q64[127:64] = { - i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], - i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], - i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], - i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], - - i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], - i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], - i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], - i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; - assign q64[63:0] = { - i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], - i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], - i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], - i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], - - i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], - i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], - i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], - i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - - assign q64_low = { - i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], - i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], - i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], - i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], - - i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], - i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], - i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], - i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - - assign q32[127:96] = { - i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], - i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], - i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], - i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]}; - assign q32[95:64] = { - i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], - i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], - i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], - i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; - assign q32[63:32] = { - i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], - i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], - i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], - i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]}; - assign q32[31:0] = { - i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], - i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], - i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], - i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; -`ifdef TEST_VERBOSE - $write("%x %x\n", q1, i); -`endif - if (cyc==1) begin - i <= 128'hed388e646c843d35de489bab2413d770; - end - if (cyc==2) begin - i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; - if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==3) begin - i <= 128'he236ddfddddbdad20a48e039c9f395b8; - if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==4) begin - i <= 128'h45e0eb7642b148537491f3da147e7f26; - if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_div.v b/test/cli/verilog/t_math_div.v deleted file mode 100644 index 9c023a1e..00000000 --- a/test/cli/verilog/t_math_div.v +++ /dev/null @@ -1,115 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - reg [255:0] a; - reg [60:0] divisor; - reg [60:0] qq; - reg [60:0] rq; - reg [60:0] qq4; - reg [60:0] rq4; - reg [60:0] qq5; - reg [60:0] rq5; - reg signed [60:0] qqs; - reg signed [60:0] rqs; - - always @* begin - qq = a[60:0] / divisor; - rq = a[60:0] % divisor; - qq4 = a[60:0] / 4; // Check power-of-two constification - rq4 = a[60:0] % 4; - qq5 = a[60:0] / 5; // Non power-of-two - rq5 = a[60:0] % 5; - qqs = $signed(a[60:0]) / $signed(divisor); - rqs = $signed(a[60:0]) % $signed(divisor); - end - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); - if (cyc==1) begin - a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - divisor <= 61'h12371; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - end - if (cyc > 1) begin - if (qq4 != {2'b0, a[60:2]}) $stop; - if (rq4 != {59'h0, a[1:0]}) $stop; - end - if (cyc==2) begin - a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - divisor <= 61'h1238123771; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - if (qq!==61'h00000403ad81c0da) $stop; - if (rq!==61'h00000000000090ec) $stop; - if (qqs!==61'h00000403ad81c0da) $stop; - if (rqs!==61'h00000000000090ec) $stop; - if (qq4 != 61'h01247cf6851f9fc9) $stop; - if (rq4 != 61'h0000000000000002) $stop; - end - if (cyc==3) begin - a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; - divisor <= 61'hf1b; - a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed - if (qq!==61'h000000000090832e) $stop; - if (rq!==61'h0000000334becc6a) $stop; - if (qqs!==61'h000000000090832e) $stop; - if (rqs!==61'h0000000334becc6a) $stop; - if (qq4 != 61'h0292380e727ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==4) begin - a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0001eda37cca1be8) $stop; - if (rq!==61'h0000000000000c40) $stop; - if (qqs!==61'h1fffcf5187c76510) $stop; - if (rqs!==61'h1ffffffffffffd08) $stop; - if (qq4 != 61'h07482923803ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==5) begin - a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0000000000000000) $stop; - if (rq!==61'h0d20a48e00f395b8) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h0d20a48e00f395b8) $stop; - end - if (cyc==6) begin - if (qq!==61'h0000000000000001) $stop; - if (rq!==61'h0d20a48e00f3869d) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h1d20a48e00f395b8) $stop; - end - // Div by zero - if (cyc==9) begin - divisor <= 61'd0; - end - if (cyc==10) begin -`ifdef verilator - if (qq !== {61{1'b0}}) $stop; - if (rq !== {61{1'b0}}) $stop; -`else - if (qq !== {61{1'bx}}) $stop; - if (rq !== {61{1'bx}}) $stop; -`endif - if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors - if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors - end - if (cyc==19) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_equal.v b/test/cli/verilog/t_math_equal.v deleted file mode 100644 index 54968a26..00000000 --- a/test/cli/verilog/t_math_equal.v +++ /dev/null @@ -1,74 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - integer _mode; - - reg _guard1; - reg [127:0] r_wide0; - reg _guard2; - wire [63:0] r_wide1; - reg _guard3; - reg _guard4; - reg _guard5; - reg _guard6; - - assign r_wide1 = r_wide0[127:64]; - - // surefire lint_off STMINI - initial _mode = 0; - - always @ (posedge clk) begin - if (_mode==0) begin - $write("[%0t] t_equal: Running\n", $time); - _guard1 <= 0; - _guard2 <= 0; - _guard3 <= 0; - _guard4 <= 0; - _guard5 <= 0; - _guard6 <= 0; - - _mode<=1; - r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; - end - else if (_mode==1) begin - _mode<=2; - // - if (5'd10 != 5'b1010) $stop; - if (5'd10 != 5'd10) $stop; - if (5'd10 != 5'd1_0) $stop; - if (5'd10 != 5'ha) $stop; - if (5'd10 != 5'o12) $stop; - if (5'd10 != 5'o1_2) $stop; - if (5'd10 != 5'B 1010) $stop; - if (5'd10 != 5'B 10_10) $stop; - if (5'd10 != 5'D10) $stop; - if (5'd10 != 5'H a) $stop; - if (5'd10 != 5 'O 12) $stop; - if (24'h29cbb8 != 24'o12345670) $stop; - if (24'h29__cbb8 != 24'o123456__70) $stop; - if (6'b111xxx !== 6'o7x) $stop; - if (6'b111??? !== 6'o7?) $stop; - if (6'b111zzz !== 6'o7z) $stop; - // - if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; - if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; - if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin - $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule diff --git a/test/cli/verilog/t_math_msvc_64.v b/test/cli/verilog/t_math_msvc_64.v deleted file mode 100644 index 27d49b27..00000000 --- a/test/cli/verilog/t_math_msvc_64.v +++ /dev/null @@ -1,75 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - - reg [89:0] in; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [89:0] out; // From test of Test.v - wire [44:0] line0; - wire [44:0] line1; - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .out (out[89:0]), - .line0 (line0[44:0]), - .line1 (line1[44:0]), - // Inputs - .clk (clk), - .in (in[89:0])); - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out); -`endif - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; - end - else if (cyc==10) begin - if (in==out) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("*-* Failed!! *-*\n"); - $finish; - end - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Outputs - line0, line1, out, - // Inputs - clk, in - ); - - input clk; - input [89:0] in; - - output reg [44:0] line0; - output reg [44:0] line1; - output reg [89:0] out; - - assign {line0,line1} = in; - always @(posedge clk) begin - out <= {line0,line1}; - end -endmodule diff --git a/test/cli/verilog/t_math_pick.v b/test/cli/verilog/t_math_pick.v deleted file mode 100644 index 03ccdb90..00000000 --- a/test/cli/verilog/t_math_pick.v +++ /dev/null @@ -1,83 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - - // Take CRC data and apply to testblock inputs - wire pick1 = crc[0]; - wire [13:0][1:0] data1 = crc[27+1:1]; - wire [3:0][2:0][1:0] data2 = crc[23+29:29]; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [15:0] [1:0] datao; // From test of Test.v - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .datao (datao/*[15:0][1:0]*/), - // Inputs - .pick1 (pick1), - .data1 (data1/*[13:0][1:0]*/), - .data2 (data2/*[2:0][3:0][1:0]*/)); - - // Aggregate outputs into a single result vector - wire [63:0] result = {32'h0, datao}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h3ff4bf0e6407b281 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module Test - ( - input logic pick1, - input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits - input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits - output logic [15:0] [1:0] datao // 16 x 2 = 32 bits - ); - // verilator lint_off WIDTH - always_comb datao[13: 0] // 28 bits - = (pick1) - ? {data1} // 28 bits - : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized - // verilator lint_on WIDTH - always_comb datao[15:14] = '0; -endmodule diff --git a/test/cli/verilog/t_math_red.v b/test/cli/verilog/t_math_red.v deleted file mode 100644 index 10cb292b..00000000 --- a/test/cli/verilog/t_math_red.v +++ /dev/null @@ -1,65 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=0; - - reg [67:0] r; - - wire and_reduce = &r; - wire or_reduce = |r; - wire xor_reduce = ^r; - wire xnor_reduce = ~^r; - wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; - - always @(posedge clk) begin -`ifdef TEST_VERBOSE - $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", - cyc, r, and_reduce, or_reduce, xor_reduce, check_equal); -`endif - cyc <= cyc + 1; - if (cyc == 1) begin - r <= 68'd0; - end - else if (cyc == 10) begin - `checkh(r, 68'h0000_0000_0000_0000_0); - `checkh(and_reduce, '0); - `checkh(or_reduce, '0); - `checkh(xor_reduce, '0); - `checkh(xnor_reduce, '1); - r <= 68'hffff_ffff_ffff_ffff_e; - end - else if (cyc == 11) begin - `checkh(r, 68'hffff_ffff_ffff_ffff_e); - `checkh(and_reduce, '0); - `checkh(or_reduce, '1); - `checkh(xor_reduce, '1); - `checkh(xnor_reduce, '0); - r <= 68'hffff_ffff_ffff_ffff_f; - end - else if (cyc == 12) begin - `checkh(r, 68'hffff_ffff_ffff_ffff_f); - `checkh(and_reduce, '1); - `checkh(or_reduce, '1); - `checkh(xor_reduce, '0); - `checkh(xnor_reduce, '1); - end - else if (cyc == 90) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - r <= 68'd0; - end - end -endmodule diff --git a/test/cli/verilog/t_math_repl.v b/test/cli/verilog/t_math_repl.v deleted file mode 100644 index 43b57e04..00000000 --- a/test/cli/verilog/t_math_repl.v +++ /dev/null @@ -1,110 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [63:0] rf; - reg [63:0] rf2; - reg [63:0] biu; - reg b; - - always @* begin - rf[63:32] = biu[63:32] & {32{b}}; - rf[31:0] = {32{b}}; - rf2 = rf; - rf2[31:0] = ~{32{b}}; - end - - reg [31:0] src1, src0, sr, mask; - wire [31:0] dualasr - = ((| src1[31:4]) - ? {{16{src0[31]}}, {16{src0[15]}}} - : ( ( sr & {2{mask[31:16]}}) - | ( {{16{src0[31]}}, {16{src0[15]}}} - & {2{~mask[31:16]}}))); - - wire [31:0] sl_mask - = (32'hffffffff << src1[4:0]); - - wire [31:0] sr_mask - = {sl_mask[0], sl_mask[1], - sl_mask[2], sl_mask[3], sl_mask[4], - sl_mask[5], sl_mask[6], sl_mask[7], - sl_mask[8], sl_mask[9], - sl_mask[10], sl_mask[11], - sl_mask[12], sl_mask[13], sl_mask[14], - sl_mask[15], sl_mask[16], - sl_mask[17], sl_mask[18], sl_mask[19], - sl_mask[20], sl_mask[21], - sl_mask[22], sl_mask[23], sl_mask[24], - sl_mask[25], sl_mask[26], - sl_mask[27], sl_mask[28], sl_mask[29], - sl_mask[30], sl_mask[31]}; - - wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; - wire [1:0] w = {2{b}}; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; -`ifdef TEST_VERBOSE - $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); -`endif - if (cyc==1) begin - biu <= 64'h12451282_abadee00; - b <= 1'b0; - src1 <= 32'h00000001; - src0 <= 32'h9a4f1235; - sr <= 32'h0f19f567; - mask <= 32'h7af07ab4; - end - if (cyc==2) begin - biu <= 64'h12453382_abad8801; - b <= 1'b1; - if (rf != 64'h0) $stop; - if (rf2 != 64'h00000000ffffffff) $stop; - src1 <= 32'h0010000f; - src0 <= 32'h028aa336; - sr <= 32'h42ad0377; - mask <= 32'h1ab3b906; - if (dualasr != 32'h8f1f7060) $stop; - if (sl_mask != 32'hfffffffe) $stop; - if (sr_mask != 32'h7fffffff) $stop; - if (widerep != '0) $stop; - end - if (cyc==3) begin - biu <= 64'h12422382_77ad8802; - b <= 1'b1; - if (rf != 64'h12453382ffffffff) $stop; - if (rf2 != 64'h1245338200000000) $stop; - src1 <= 32'h0000000f; - src0 <= 32'h5c158f71; - sr <= 32'h7076c40a; - mask <= 32'h33eb3d44; - if (dualasr != 32'h0000ffff) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - if (widerep != '1) $stop; - end - if (cyc==4) begin - if (rf != 64'h12422382ffffffff) $stop; - if (rf2 != 64'h1242238200000000) $stop; - if (dualasr != 32'h3062cc1e) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - $write("*-* All Finished *-*\n"); - if (widerep != '1) $stop; - $finish; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_shift.v b/test/cli/verilog/t_math_shift.v deleted file mode 100644 index e8f9379c..00000000 --- a/test/cli/verilog/t_math_shift.v +++ /dev/null @@ -1,239 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - ign, ign2, ign3, ign4, ign4s, - // Inputs - clk - ); - - input clk; - output [31:0] ign; - output [3:0] ign2; - output [11:0] ign3; - - parameter [95:0] P6 = 6; - localparam P64 = (1 << P6); - - // verilator lint_off WIDTH - localparam [4:0] PBIG23 = 1'b1 << ~73'b0; - localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; - // verilator lint_on WIDTH - - reg [31:0] iright; - reg signed [31:0] irights; - reg [31:0] ileft; - reg [P64-1:0] qright; - reg signed [P64-1:0] qrights; - reg [P64-1:0] qleft; - reg [95:0] wright; - reg signed [95:0] wrights; - reg [95:0] wleft; - - reg [31:0] q_iright; - reg signed [31:0] q_irights; - reg [31:0] q_ileft; - reg [P64-1:0] q_qright; - reg signed [P64-1:0] q_qrights; - reg [P64-1:0] q_qleft; - reg [95:0] q_wright; - reg signed [95:0] q_wrights; - reg [95:0] q_wleft; - - - reg [31:0] w_iright; - reg signed [31:0] w_irights; - reg [31:0] w_ileft; - reg [P64-1:0] w_qright; - reg signed [P64-1:0] w_qrights; - reg [P64-1:0] w_qleft; - reg [95:0] w_wright; - reg signed [95:0] w_wrights; - reg [95:0] w_wleft; - - reg [31:0] iamt; - reg [63:0] qamt; - reg [95:0] wamt; - - assign ign = {31'h0, clk} >>> 4'bx; // bug760 - assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 - assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, - iamt[1:0] >> {11{iamt[5:2]}}, - $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, - $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, - iamt[1:0] << {22{iamt[5:2]}}, - iamt[1:0] << {11{iamt[5:2]}}}; - - wire [95:0] wamtt = {iamt,iamt,iamt}; - output wire [95:0] ign4; - assign ign4 = wamtt >> {11{iamt[5:2]}}; - output wire signed [95:0] ign4s; - assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; - - always @* begin - iright = 32'h819b018a >> iamt; - irights = 32'sh819b018a >>> signed'(iamt); - ileft = 32'h819b018a << iamt; - qright = 64'hf784bf8f_12734089 >> iamt; - qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); - qleft = 64'hf784bf8f_12734089 << iamt; - wright = 96'hf784bf8f_12734089_190abe48 >> iamt; - wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); - wleft = 96'hf784bf8f_12734089_190abe48 << iamt; - - q_iright = 32'h819b018a >> qamt; - q_irights = 32'sh819b018a >>> signed'(qamt); - q_ileft = 32'h819b018a << qamt; - q_qright = 64'hf784bf8f_12734089 >> qamt; - q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); - q_qleft = 64'hf784bf8f_12734089 << qamt; - q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; - q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); - q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; - - w_iright = 32'h819b018a >> wamt; - w_irights = 32'sh819b018a >>> signed'(wamt); - w_ileft = 32'h819b018a << wamt; - w_qright = 64'hf784bf8f_12734089 >> wamt; - w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); - w_qleft = 64'hf784bf8f_12734089 << wamt; - w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; - w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); - w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; - end - - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; -`ifdef TEST_VERBOSE - $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); -`endif - if (cyc==1) begin - iamt <= 0; - qamt <= 0; - wamt <= 0; - if (P64 != 64) $stop; - if (5'b10110>>2 != 5'b00101) $stop; - if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness - if (5'b10110<<2 != 5'b11000) $stop; - if (5'b10110<<<2 != 5'b11000) $stop; - if (5'sb10110>>2 != 5'sb00101) $stop; - if (5'sb10110>>>2 != 5'sb11101) $stop; - if (5'sb10110<<2 != 5'sb11000) $stop; - if (5'sb10110<<<2 != 5'sb11000) $stop; - // Allow >64 bit shifts if the shift amount is a constant - if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; - end - if (cyc==2) begin - iamt <= 28; - qamt <= 28; - wamt <= 28; - if (ileft != 32'h819b018a) $stop; - if (iright != 32'h819b018a) $stop; - if (irights != 32'h819b018a) $stop; - if (qleft != 64'hf784bf8f_12734089) $stop; - if (qright != 64'hf784bf8f_12734089) $stop; - if (qrights != 64'hf784bf8f_12734089) $stop; - if (wleft != 96'hf784bf8f12734089190abe48) $stop; - if (wright != 96'hf784bf8f12734089190abe48) $stop; - if (wrights != 96'hf784bf8f12734089190abe48) $stop; - end - if (cyc==3) begin - iamt <= 31; - qamt <= 31; - wamt <= 31; - if (ileft != 32'ha0000000) $stop; - if (iright != 32'h8) $stop; - if (irights != 32'hfffffff8) $stop; - if (qleft != 64'hf127340890000000) $stop; - if (qright != 64'h0000000f784bf8f1) $stop; - if (qrights != 64'hffffffff784bf8f1) $stop; - if (wleft != 96'hf12734089190abe480000000) $stop; - if (wright != 96'h0000000f784bf8f127340891) $stop; - if (wrights != 96'hffffffff784bf8f127340891) $stop; - end - if (cyc==4) begin - iamt <= 32; - qamt <= 32; - wamt <= 32; - if (ileft != 32'h0) $stop; - if (iright != 32'h1) $stop; - if (qleft != 64'h8939a04480000000) $stop; - if (qright != 64'h00000001ef097f1e) $stop; - end - if (cyc==5) begin - iamt <= 33; - qamt <= 33; - wamt <= 33; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h1273408900000000) $stop; - if (qright != 64'h00000000f784bf8f) $stop; - end - if (cyc==6) begin - iamt <= 64; - qamt <= 64; - wamt <= 64; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h24e6811200000000) $stop; - if (qright != 64'h000000007bc25fc7) $stop; - end - if (cyc==7) begin - iamt <= 128; - qamt <= 128; - wamt <= 128; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h0) $stop; - if (qright != 64'h0) $stop; - end - if (cyc==8) begin - iamt <= 100; - qamt <= {32'h10, 32'h0}; - wamt <= {32'h10, 64'h0}; - if (ileft != '0) $stop; - if (iright != '0) $stop; - if (irights != '1) $stop; - if (qleft != '0) $stop; - if (qright != '0) $stop; - if (qrights != '1) $stop; - if (wleft != '0) $stop; - if (wright != '0) $stop; - if (wrights != '1) $stop; - end - if (cyc==19) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - // General rule to test all q's - if (cyc != 0) begin - if (ileft != q_ileft) $stop; - if (iright != q_iright) $stop; - if (irights != q_irights) $stop; - if (qleft != q_qleft) $stop; - if (qright != q_qright) $stop; - if (qrights != q_qrights) $stop; - if (wleft != q_wleft) $stop; - if (wright != q_wright) $stop; - if (wrights != q_wrights) $stop; - - if (ileft != w_ileft) $stop; - if (iright != w_iright) $stop; - if (irights != w_irights) $stop; - if (qleft != w_qleft) $stop; - if (qright != w_qright) $stop; - if (qrights != w_qrights) $stop; - if (wleft != w_wleft) $stop; - if (wright != w_wright) $stop; - if (wrights != w_wrights) $stop; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_shift_rep.v b/test/cli/verilog/t_math_shift_rep.v deleted file mode 100644 index cd0011fe..00000000 --- a/test/cli/verilog/t_math_shift_rep.v +++ /dev/null @@ -1,78 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - - //bug765; disappears if add this wire - //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values - wire [7:0] a = crc[7:0]; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [15:0] y; // From test of Test.v - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .y (y[15:0]), - // Inputs - .a (a[7:0])); - - // Aggregate outputs into a single result vector - wire [63:0] result = {48'h0, y}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Outputs - y, - // Inputs - a - ); - input signed [7:0] a; - output [15:0] y; - // verilator lint_off WIDTH - assign y = ~66'd0 <<< {4{a}}; - // verilator lint_on WIDTH -endmodule diff --git a/test/cli/verilog/t_math_shiftrs.v b/test/cli/verilog/t_math_shiftrs.v deleted file mode 100644 index d89c637d..00000000 --- a/test/cli/verilog/t_math_shiftrs.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg signed [64+15:0] data; - integer i; - integer b; - reg signed [64+15:0] srs; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==2) begin - data <= 80'h0; - data[75] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==3) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b==(75-i) || b==(10-i))) $stop; - end - end - end - if (cyc==10) begin - data <= 80'h0; - data[79] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==12) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; - end - end - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test/cli/verilog/t_math_vliw.v b/test/cli/verilog/t_math_vliw.v deleted file mode 100644 index bf6ab729..00000000 --- a/test/cli/verilog/t_math_vliw.v +++ /dev/null @@ -1,104 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=0; - reg [7:0] crc; - reg [223:0] sum; - - wire [255:0] mglehy = {32{~crc}}; - wire [215:0] drricx = {27{crc}}; - wire [15:0] apqrli = {2{~crc}}; - wire [2:0] szlfpf = crc[2:0]; - wire [15:0] dzosui = {2{crc}}; - wire [31:0] zndrba = {16{crc[1:0]}}; - wire [223:0] bxiouf; - - vliw vliw ( - // Outputs - .bxiouf (bxiouf), - // Inputs - .mglehy (mglehy[255:0]), - .drricx (drricx[215:0]), - .apqrli (apqrli[15:0]), - .szlfpf (szlfpf[2:0]), - .dzosui (dzosui[15:0]), - .zndrba (zndrba[31:0])); - - always @ (posedge clk) begin - cyc <= cyc + 1; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==0) begin - // Setup - crc <= 8'hed; - sum <= 224'h0; - end - else if (cyc<90) begin - //$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf); - sum <= {sum[222:0],sum[223]} ^ bxiouf; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); - if (crc !== 8'b01110000) $stop; - if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module vliw ( - input[255:0] mglehy, - input[215:0] drricx, - input[15:0] apqrli, - input[2:0] szlfpf, - input[15:0] dzosui, - input[31:0] zndrba, - output wire [223:0] bxiouf - ); - - wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) - | ({29{apqrli}} & {mglehy[247:0], drricx}); - wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) - | ({21{dzosui}} & zhknfc[335:0]); - wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; - wire [223:0] rzyeut = viuvoc[335:112]; - assign bxiouf = {rzyeut[7:0], - rzyeut[15:8], - rzyeut[23:16], - rzyeut[31:24], - rzyeut[39:32], - rzyeut[47:40], - rzyeut[55:48], - rzyeut[63:56], - rzyeut[71:64], - rzyeut[79:72], - rzyeut[87:80], - rzyeut[95:88], - rzyeut[103:96], - rzyeut[111:104], - rzyeut[119:112], - rzyeut[127:120], - rzyeut[135:128], - rzyeut[143:136], - rzyeut[151:144], - rzyeut[159:152], - rzyeut[167:160], - rzyeut[175:168], - rzyeut[183:176], - rzyeut[191:184], - rzyeut[199:192], - rzyeut[207:200], - rzyeut[215:208], - rzyeut[223:216]}; - -endmodule diff --git a/test/cli/verilog/t_mem_fifo.v b/test/cli/verilog/t_mem_fifo.v deleted file mode 100644 index 8702c496..00000000 --- a/test/cli/verilog/t_mem_fifo.v +++ /dev/null @@ -1,111 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - integer cyc; initial cyc=0; - reg [63:0] crc; - - wire [65:0] outData; // From fifo of fifo.v - wire [15:0] inData = crc[15:0]; - wire [1:0] inWordPtr = crc[17:16]; - wire wrEn = crc[20]; - wire [1:0] wrPtr = crc[33:32]; - wire [1:0] rdPtr = crc[34:33]; - - fifo fifo ( - // Outputs - .outData (outData[65:0]), - // Inputs - .clk (clk), - .inWordPtr (inWordPtr[1:0]), - .inData (inData[15:0]), - .rdPtr (rdPtr), - .wrPtr (wrPtr), - .wrEn (wrEn)); - - always @ (posedge clk) begin - //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc==90) begin - if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; - end - else if (cyc==91) begin - if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; - end - else if (cyc==92) begin - if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; - end - else if (cyc==93) begin - if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; - end - else if (cyc==94) begin - if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module fifo (/*AUTOARG*/ - // Outputs - outData, - // Inputs - clk, inWordPtr, inData, wrPtr, rdPtr, wrEn - ); - - parameter fifoDepthLog2 = 1; - parameter fifoDepth = 1<=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin - narrow <= ({narrow[6:0], narrow[7]^narrow[0]} - ^ {memn[index0][index1][index2]}); - wread = memw[index0][index1][index2]; - wreadb = memw[index0][index1][index2][2]; - wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); - //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); - end - // We may write past bounds of memory - memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; - memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; - memw[index0][index1][index2] <= {~crc[7:0],crc}; - //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); - cstyle[cyc[0]] <= cyc[2:0]; - if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; - end - else if (cyc==90) begin - memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; - end - else if (cyc==91) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide); - if (crc != 64'h65e3bddcd9bc2750) $stop; - if (narrow != 8'hca) $stop; - if (wide != 72'h4edafed31ba6873f73) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule diff --git a/test/cli/verilog/t_mem_packed.v b/test/cli/verilog/t_mem_packed.v deleted file mode 100644 index 52a38bf9..00000000 --- a/test/cli/verilog/t_mem_packed.v +++ /dev/null @@ -1,180 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - //Simple debug: - //wire [1:1] wir_a [3:3] [2:2]; //11 - //logic [1:1] log_a [3:3] [2:2]; //12 - //wire [3:3] [2:2] [1:1] wir_p; //13 - //logic [3:3] [2:2] [1:1] log_p; //14 - - integer cyc; initial cyc = 0; -`ifdef IVERILOG - reg [7:0] arr [3:0]; - wire [7:0] arr_w [3:0]; -`else - reg [3:0] [7:0] arr; - wire [3:0] [7:0] arr_w; -`endif - reg [7:0] sum; - reg [7:0] sum_w; - integer i0; - - initial begin - for (i0=0; i0<5; i0=i0+1) begin - arr[i0] = 1 << (i0[1:0]*2); - end - end - - assign arr_w = arr; - - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - sum <= 0; - sum_w <= 0; - end - else if (cyc >= 10 && cyc < 14) begin - sum <= sum + arr[cyc-10]; - - sum_w <= sum_w + arr_w[cyc-10]; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum); - if (sum != 8'h55) $stop; - if (sum != sum_w) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - - // Test ordering of packed dimensions - logic [31:0] data_out; - logic [31:0] data_out2; - logic [0:0] [2:0] [31:0] data_in; - logic [31:0] data_in2 [0:0] [2:0]; - assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; - assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; - - logic [31:0] last_data_out; - always @ (posedge clk) begin - if (cyc <= 2) begin - data_in[0][0] <= 0; - data_in[0][1] <= 0; - data_in[0][2] <= 0; - data_in2[0][0] <= 0; - data_in2[0][1] <= 0; - data_in2[0][2] <= 0; - end - else if (cyc > 2 && cyc < 99) begin - data_in[0][0] <= data_in[0][0] + 1; - data_in[0][1] <= data_in[0][1] + 1; - data_in[0][2] <= data_in[0][2] + 1; - data_in2[0][0] <= data_in2[0][0] + 1; - data_in2[0][1] <= data_in2[0][1] + 1; - data_in2[0][2] <= data_in2[0][2] + 1; - last_data_out <= data_out; -`ifdef TEST_VERBOSE - $write("data_out %0x %0x\n", data_out, last_data_out); -`endif - if (cyc > 4 && data_out != last_data_out + 3) $stop; - if (cyc > 4 && data_out != data_out2) $stop; - end - end - - // Test for mixed implicit/explicit dimensions and all implicit packed - bit [3:0][7:0][1:0] vld [1:0][1:0]; - bit [3:0][7:0][1:0] vld2; - - // There are specific nodes for Or, Xor, Xnor and And - logic vld_or; - logic vld2_or; - assign vld_or = |vld[0][0]; - assign vld2_or = |vld2; - - logic vld_xor; - logic vld2_xor; - assign vld_xor = ^vld[0][0]; - assign vld2_xor = ^vld2; - - logic vld_xnor; - logic vld2_xnor; - assign vld_xnor = ~^vld[0][0]; - assign vld2_xnor = ~^vld2; - - logic vld_and; - logic vld2_and; - assign vld_and = &vld[0][0]; - assign vld2_and = &vld2; - - // Bit reductions should be cloned, other unary operations should clone the - // entire assign. - bit [3:0][7:0][1:0] not_lhs; - bit [3:0][7:0][1:0] not_rhs; - assign not_lhs = ~not_rhs; - - // Test an AstNodeUniop that shouldn't be expanded - bit [3:0][7:0][1:0] vld2_inv; - assign vld2_inv = ~vld2; - - initial begin - for (int i=0; i<4; i=i+2) begin - for (int j=0; j<8; j=j+2) begin - vld[0][0][i][j] = 2'b00; - vld[0][0][i+1][j+1] = 2'b00; - vld2[i][j] = 2'b00; - vld2[i+1][j+1] = 2'b00; - not_rhs[i][j] = i[1:0]; - not_rhs[i+1][j+1] = i[1:0]; - end - end - end - - - logic [3:0] expect_cyc; initial expect_cyc = 'd15; - - always @(posedge clk) begin - expect_cyc <= expect_cyc + 1; - for (int i=0; i<4; i=i+1) begin - for (int j=0; j<8; j=j+1) begin - vld[0][0][i][j] <= vld[0][0][i][j] + 1; - vld2[i][j] <= vld2[i][j] + 1; - if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; - not_rhs[i][j] <= not_rhs[i][j] + 1; - end - end - if (cyc % 8 == 0) begin - vld[0][0][0][0] <= vld[0][0][0][0] - 1; - vld2[0][0] <= vld2[0][0] - 1; - end - if (expect_cyc < 8 && !vld_xor) $stop; - else if (expect_cyc > 7 && vld_xor) $stop; - - if (expect_cyc < 8 && vld_xnor) $stop; - else if (expect_cyc > 7 && !vld_xnor) $stop; - - if (expect_cyc == 15 && vld_or) $stop; - else if (expect_cyc == 11 && vld_or) $stop; - else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; - - if (expect_cyc == 10 && !vld_and) $stop; - else if (expect_cyc == 14 && !vld_and) $stop; - else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; - - if (vld_xor != vld2_xor) $stop; - if (vld_xnor != vld2_xnor) $stop; - if (vld_or != vld2_or) $stop; - if (vld_and != vld2_and) $stop; - end - -endmodule diff --git a/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v b/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v deleted file mode 100644 index 6c7f1a62..00000000 --- a/test/cli/verilog/t_no_sel_assign_merge_in_cpp.v +++ /dev/null @@ -1,14 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t_no_sel_assign_merge_in_cpp ( - input wire [(8*39)-1:0] d_i, - output wire [(8*32)-1:0] d_o -); - for (genvar i = 0; i < 8; i = i + 1) begin - assign d_o[i*32 +: 32] = d_i[i*39 +: 32]; - end -endmodule diff --git a/test/cli/verilog/t_order_comboloop.v b/test/cli/verilog/t_order_comboloop.v deleted file mode 100644 index b9b3d2fe..00000000 --- a/test/cli/verilog/t_order_comboloop.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - integer cyc; initial cyc=1; - - // verilator lint_off LATCH - // verilator lint_off UNOPT - // verilator lint_off UNOPTFLAT - reg [31:0] runner; initial runner = 5; - reg [31:0] runnerm1; - reg [59:0] runnerq; - reg [89:0] runnerw; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin -`ifdef verilator - if (runner != 0) $stop; // Initial settlement failed -`endif - end - if (cyc==2) begin - runner = 20; - runnerq = 60'h0; - runnerw = 90'h0; - end - if (cyc==3) begin - if (runner != 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - - // This forms a "loop" where we keep going through the always till runner=0 - // This isn't "regular" beh code, but ensures our change detection is working properly - always @ (/*AS*/runner) begin - runnerm1 = runner - 32'd1; - end - - always @ (/*AS*/runnerm1) begin - if (runner > 0) begin - runner = runnerm1; - runnerq = runnerq - 60'd1; - runnerw = runnerw - 90'd1; - $write ("[%0t] runner=%d\n", $time, runner); - end - end - -endmodule diff --git a/test/cli/verilog/t_param_array5.v b/test/cli/verilog/t_param_array5.v deleted file mode 100644 index 356c051a..00000000 --- a/test/cli/verilog/t_param_array5.v +++ /dev/null @@ -1,39 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -//bug1578 -module t; - parameter N = 4; - - typedef logic array_t[N]; - - parameter array_t MASK = mask_array(); - //TODO bug1578: parameter MASK = mask_array(); - - function array_t mask_array(); - for(int i = 0; i < N; i++) begin - mask_array[i] = i[0]; - end - endfunction - - array_t norm; - - initial begin - if (N != 4) $stop; - norm = mask_array(); - if (norm[0] != 1'b0) $stop; - if (norm[1] != 1'b1) $stop; - if (norm[2] != 1'b0) $stop; - if (norm[3] != 1'b1) $stop; - if (MASK[0] != 1'b0) $stop; - if (MASK[1] != 1'b1) $stop; - if (MASK[2] != 1'b0) $stop; - if (MASK[3] != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test/cli/verilog/t_select_little.v b/test/cli/verilog/t_select_little.v deleted file mode 100644 index 2b7b9e93..00000000 --- a/test/cli/verilog/t_select_little.v +++ /dev/null @@ -1,75 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - - // verilator lint_off LITENDIAN - wire [10:41] sel2 = crc[31:0]; - wire [10:100] sel3 = {crc[26:0],crc}; - - wire out20 = sel2[{1'b0,crc[3:0]} + 11]; - wire [3:0] out21 = sel2[13 : 16]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; - - wire out30 = sel3[{2'b0,crc[3:0]} + 11]; - wire [3:0] out31 = sel3[13 : 16]; - wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; - - // Aggregate outputs into a single result vector - wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; - - reg [19:50] sel1; - initial begin - // Path clearing - // 122333445 - // 826048260 - sel1 = 32'h12345678; - if (sel1 != 32'h12345678) $stop; - if (sel1[47 : 50] != 4'h8) $stop; - if (sel1[31 : 34] != 4'h4) $stop; - if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] - if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] - end - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33); - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h28bf65439eb12c00 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule diff --git a/test/cli/verilog/t_unroll_forfor.v b/test/cli/verilog/t_unroll_forfor.v deleted file mode 100644 index a37ad75e..00000000 --- a/test/cli/verilog/t_unroll_forfor.v +++ /dev/null @@ -1,35 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This files is used to generated the following error: -// %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Jan Egil Ruud. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk, in - ); - input clk; - input [71:0] in; - - reg [71:0] in_tmp; - - localparam [71:0] TEST_PARAM = {72{1'b0}}; - - // Test loop - always @* - begin: testmap - byte i, j; - // bug1044 - for ( i = 0; i < 9; i = i + 1 ) - // verilator lint_off WIDTH - for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin - in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; - end - // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test/cli/verilog/t_var_assign_landr.v b/test/cli/verilog/t_var_assign_landr.v deleted file mode 100644 index 4713eea8..00000000 --- a/test/cli/verilog/t_var_assign_landr.v +++ /dev/null @@ -1,91 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [255:0] sum; - - // Take CRC data and apply to testblock inputs - wire [127:0] in = {~crc[63:0], crc[63:0]}; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [127:0] o1; // From test of Test.v - wire [127:0] o2; // From test of Test.v - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .o1 (o1[127:0]), - .o2 (o2[127:0]), - // Inputs - .in (in[127:0])); - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x %x\n",$time, cyc, crc, o1, o2); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Outputs - o1, o2, - // Inputs - in - ); - - input [127:0] in; - output logic [127:0] o1; - output logic [127:0] o2; - - always_comb begin: b_test - logic [127:0] tmpp; - logic [127:0] tmp; - tmp = '0; - tmpp = '0; - - tmp[63:0] = in[63:0]; - tmpp[63:0] = in[63:0]; - - tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; - tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; - - o1 = tmp; - o2 = tmpp; - end - -endmodule diff --git a/test/cli/verilog/t_var_pinsizes.v b/test/cli/verilog/t_var_pinsizes.v deleted file mode 100644 index 22ac179c..00000000 --- a/test/cli/verilog/t_var_pinsizes.v +++ /dev/null @@ -1,68 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -// Also check that SystemC is ordering properly -// verilator lint_on IMPERFECTSCH - -module t (/*AUTOARG*/ - // Outputs - o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt, - // Inputs - clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt - ); - - input clk; - - input i1; - input [7:0] i8; - input [15:0] i16; - input [31:0] i32; - input [63:0] i64; - input [64:0] i65; - input [127:0] i128; - input [512:0] i513; - input i1a2 [1:0]; - input [93:0] i94a3 [2:0]; - - output logic o1; - output logic [7:0] o8; - output logic [15:0] o16; - output logic [31:0] o32; - output logic [63:0] o64; - output logic [64:0] o65; - output logic [127:0] o128; - output logic [512:0] o513; - output logic o1a2 [1:0]; - output logic [93:0] o94a3 [2:0]; - - input [0:0] ibv1 /*verilator sc_bv*/; - input [15:0] ibv16 /*verilator sc_bv*/; - input [0:0] ibv1_vlt; - input [15:0] ibv16_vlt; - - output logic [0:0] obv1 /*verilator sc_bv*/; - output logic [15:0] obv16 /*verilator sc_bv*/; - output logic [0:0] obv1_vlt; - output logic [15:0] obv16_vlt; - - always @ (posedge clk) begin - o1 <= i1; - o8 <= i8; - o16 <= i16; - o32 <= i32; - o64 <= i64; - o65 <= i65; - o128 <= i128; - o513 <= i513; - obv1 <= ibv1; - obv16 <= ibv16; - obv1_vlt <= ibv1_vlt; - obv16_vlt <= ibv16_vlt; - o1a2 <= i1a2; - o94a3 <= i94a3; - end - -endmodule