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arm: started on fpu insns
This commit is contained in:
Steven Hugg
parent
9142328468
commit
47a7aa5a83
@ -105,6 +105,7 @@ export interface ARMCoreState {
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bankedSPSRs: number[],
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sfprs: number[],
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dfprs: number[],
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ifprs: number[],
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cycles: number,
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instructionWidth: 2 | 4
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}
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@ -113,6 +114,7 @@ interface ARMCoreType {
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gprs: Int32Array;
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sfprs: Float32Array;
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dfprs: Float64Array;
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ifprs: Int32Array;
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PC: number;
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SP: number;
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LR: number;
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@ -1769,6 +1771,201 @@ ARMCoreArm.prototype.constructUMULLS = function(rd, rn, rs, rm, condOp) {
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};
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};
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ARMCoreArm.prototype.constructVFP3Register = function(condOp, opcode, nOperandReg, destReg, number, opcode2, mOperandReg) {
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var cpu : ARMCoreType = this.cpu;
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var gprs = cpu.gprs;
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var sregs = cpu.sfprs;
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var dregs = cpu.dfprs;
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var iregs = cpu.ifprs;
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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switch (opcode) {
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case 1: // VMOV
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switch (opcode2) {
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case 0:
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gprs[destReg] = iregs[nOperandReg];
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return;
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}
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break;
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case 2: // VMUL
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switch (opcode2) {
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case 0:
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sregs[destReg] = sregs[nOperandReg] * sregs[mOperandReg];
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return;
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}
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break;
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case 3: // VADD/VSUB
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switch (opcode2) {
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case 0:
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sregs[destReg] = sregs[nOperandReg] + sregs[mOperandReg];
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return;
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case 2:
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sregs[destReg] = sregs[nOperandReg] - sregs[mOperandReg];
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return;
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}
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break;
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case 8: // VDIV
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switch (opcode2) {
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case 0:
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sregs[destReg] = sregs[nOperandReg] / sregs[mOperandReg];
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return;
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}
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break;
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}
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console.log("Unsupported instruction: " + hex(opcode) + " " + hex(opcode2));
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};
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};
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/*
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if opc2 != '000' && !(opc2 IN "10x") then SEE "Related encodings";
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to_integer = (opc2<2> == '1'); dp_operation = (sz == 1);
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if to_integer then
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unsigned = (opc2<0> == '0'); round_zero = (op == '1');
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d = UInt(Vd:D); m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
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else
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unsigned = (op == '0'); round_nearest = FALSE; // FALSE selects FPSCR rounding
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m = UInt(Vm:M); d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
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if ConditionPassed() then
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EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
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if to_integer then
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if dp_operation then
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S[d] = FPToFixed(D[m], 32, 0, unsigned, round_zero, TRUE);
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else
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S[d] = FPToFixed(S[m], 32, 0, unsigned, round_zero, TRUE);
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else
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if dp_operation then
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D[d] = FixedToFP(S[m], 64, 0, unsigned, round_nearest, TRUE);
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else
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S[d] = FixedToFP(S[m], 32, 0, unsigned, round_nearest, TRUE);
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*/
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ARMCoreArm.prototype.constructVCVT = function(condOp, D, opc2, Vd, sz, op, M, Vm) {
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var cpu : ARMCoreType = this.cpu;
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var sregs = cpu.sfprs;
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var dregs = cpu.dfprs;
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var iregs = cpu.ifprs;
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var to_integer = (opc2 & 0x4) != 0;
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var dp_operation = (sz & 1) != 0;
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var unsigned = (opc2 & 0x1) == 0;
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var round_zero = false;
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var round_nearest = false;
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if (to_integer) {
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unsigned = (opc2 & 0x1) == 0;
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round_zero = (op & 0x1) != 0;
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} else {
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unsigned = (op & 0x1) == 0;
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round_nearest = false;
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}
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//console.log("VCVT: " + hex(D) + " " + hex(opc2) + " " + hex(Vd) + " " + hex(sz) + " " + hex(op) + " " + hex(M) + " " + hex(Vm) + " " + to_integer + " " + unsigned);
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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var src : number;
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var dest : number;
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// get source
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if (to_integer && dp_operation) {
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src = dregs[M];
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} else if (to_integer) {
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src = sregs[M];
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} else {
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src = iregs[M];
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}
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// convert
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if (to_integer) {
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dest = round_zero ? Math.floor(src) : Math.round(src);
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} else {
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dest = src;
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}
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// store result
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if (to_integer) {
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iregs[D] = dest;
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} else if (dp_operation) {
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dregs[D] = dest;
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} else {
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sregs[D] = dest;
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}
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};
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}
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ARMCoreArm.prototype.constructVLDR = function(condOp, destReg, address, single_reg) {
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var cpu : ARMCoreType = this.cpu;
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var iregs = cpu.ifprs;
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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let addr = address();
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if (single_reg) {
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iregs[destReg] = cpu.mmu.load32(addr);
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} else {
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iregs[destReg*2] = cpu.mmu.load32(addr);
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iregs[destReg*2+1] = cpu.mmu.load32(addr+4);
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}
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cpu.mmu.wait32(addr);
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cpu.mmu.wait32(cpu.gprs[ARMRegs.PC]);
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};
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};
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ARMCoreArm.prototype.constructVSTR = function(condOp, srcReg, address, single_reg) {
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var cpu : ARMCoreType = this.cpu;
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var iregs = cpu.ifprs;
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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let addr = address();
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if (single_reg) {
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cpu.mmu.store32(addr, iregs[srcReg]);
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} else {
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cpu.mmu.store32(addr, iregs[srcReg*2]);
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cpu.mmu.store32(addr+4, iregs[srcReg*2+1]);
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}
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cpu.mmu.wait32(addr);
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cpu.mmu.wait32(cpu.gprs[ARMRegs.PC]);
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};
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}
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ARMCoreArm.prototype.constructVPUSH = function(condOp, d, regs, single_regs) {
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var cpu : ARMCoreType = this.cpu;
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var iregs = cpu.ifprs;
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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let addr = cpu.gprs[ARMRegs.SP] - regs * 4;
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cpu.gprs[ARMRegs.SP] = addr;
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for (let i = 0; i < regs; ++i) {
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cpu.mmu.store32(addr, iregs[d+i]);
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addr += 4;
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}
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};
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}
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ARMCoreArm.prototype.constructVPOP = function(condOp, d, regs, single_regs) {
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var cpu : ARMCoreType = this.cpu;
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var iregs = cpu.ifprs;
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return function() {
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cpu.mmu.waitPrefetch32(cpu.gprs[ARMRegs.PC]);
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if (condOp && !condOp()) {
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return;
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}
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let addr = cpu.gprs[ARMRegs.SP];
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cpu.gprs[ARMRegs.SP] += regs * 4;
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for (let i = 0; i < regs; ++i) {
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iregs[d+i] = cpu.mmu.load32(addr);
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addr += 4;
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}
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};
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}
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///////////////////////////////////////////////////////////////////////////
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function ARMCoreThumb(cpu) {
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@ -2669,6 +2866,7 @@ function ARMCore() {
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this.gprs = new Int32Array(16);
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this.dfprs = new Float64Array(16);
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this.sfprs = new Float32Array(this.dfprs.buffer); // regs shared with dfprs
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this.ifprs = new Int32Array(this.dfprs.buffer); // regs shared with dfprs
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};
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ARMCore.prototype.resetCPU = function(startOffset) {
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@ -2783,6 +2981,7 @@ ARMCore.prototype.freeze = function() : ARMCoreState {
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],
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'sfprs': this.sfprs.slice(),
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'dfprs': this.dfprs.slice(),
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'ifprs': this.ifprs.slice(),
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'mode': this.mode,
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'cpsrI': this.cpsrI,
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'cpsrF': this.cpsrF,
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@ -2864,8 +3063,7 @@ ARMCore.prototype.defrost = function(frost: ARMCoreState) {
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this.gprs[14] = frost.gprs[14];
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this.gprs[15] = frost.gprs[15];
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//this.sfprs.set(frost.sfprs);
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this.dfprs.set(frost.dfprs); // regs shared with sfprs
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this.ifprs.set(frost.ifprs); // regs shared with sfprs
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this.mode = frost.mode;
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this.cpsrI = frost.cpsrI;
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@ -3689,24 +3887,66 @@ ARMCore.prototype.compileArm = function(instruction) {
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break;
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case 0x0C000000:
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// Coprocessor data transfer
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// VSTM, VSTMDB, VSTMIA
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if ((instruction & 0x0c100f00) == 0x0c000a00) {
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// TODO
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op = this.armCompiler.constructNOP();
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/* TODO
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const rn = (instruction & 0x000F0000) >> 16;
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const vd = (instruction & 0x0000F000) >> 12;
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const imm = instruction & 0x000000FF;
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const writeback = instruction & 0x00200000;
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const increment = instruction & 0x00800000;
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const load = instruction & 0x00100000;
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const user = instruction & 0x00400000;
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op.writesPC = false;
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*/
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var load = instruction & 0x00100000;
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var w = instruction & 0x00200000;
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var user = instruction & 0x00400000;
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var u = instruction & 0x00800000;
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var p = instruction & 0x01000000;
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var rn = (instruction & 0x000F0000) >> 16;
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var crd = (instruction & 0x0000F000) >> 12;
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var cpnum = (instruction & 0x00000F00) >> 8;
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var immediate = instruction & 0x000000FF;
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var cond = (instruction >> 28) & 0xf;
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var condOp = this.conds[cond];
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// VPUSH, VPOP
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if ((instruction & 0x0fbf0f00) == 0x0d2d0a00) {
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op = this.armCompiler.constructVPUSH(condOp, (crd<<1)|(user?1:0), immediate, true);
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}
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else if ((instruction & 0x0fbf0f00) == 0x0d2d0b00) {
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op = this.armCompiler.constructVPUSH(condOp, ((user?16:0)|crd)*2, immediate, false);
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}
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else if ((instruction & 0x0fbf0f00) == 0x0cbd0a00) {
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op = this.armCompiler.constructVPOP(condOp, (crd<<1)|(user?1:0), immediate, true);
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}
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else if ((instruction & 0x0fbf0f00) == 0x0cbd0b00) {
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op = this.armCompiler.constructVPOP(condOp, ((user?16:0)|crd)*2, immediate, false);
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}
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// VLDR, VSTR
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else if ((instruction & 0x0f200f00) == 0x0d000a00) {
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immediate *= 4;
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if (!u) immediate = -immediate;
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var overlap = false;
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var d = (crd<<1)|(user?1:0);
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var address : AddressFunction;
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if (w) {
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address = this.armCompiler.constructAddressingMode4Writeback(immediate, offset, rn, overlap);
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} else {
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address = this.armCompiler.constructAddressingMode4(immediate, rn);
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}
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if (load) {
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op = this.armCompiler.constructVLDR(condOp, crd, address, true);
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} else {
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op = this.armCompiler.constructVSTR(condOp, crd, address, true);
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}
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} else if ((instruction & 0x0f200f00) == 0x0d000b00) {
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immediate *= 4;
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if (!u) immediate = -immediate;
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var overlap = false;
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var d = ((user?16:0)|crd)*2;
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var address : AddressFunction;
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if (w) {
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address = this.armCompiler.constructAddressingMode4Writeback(immediate, offset, rn, overlap);
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} else {
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address = this.armCompiler.constructAddressingMode4(immediate, rn);
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}
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if (load) {
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op = this.armCompiler.constructVLDR(condOp, crd, address, false);
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} else {
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op = this.armCompiler.constructVSTR(condOp, crd, address, false);
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}
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else if ((instruction & 0x0c100f00) == 0x0c100a00) {
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// TODO: VSTR, VLDR
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op = this.armCompiler.constructNOP();
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}
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break;
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case 0x0E000000:
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@ -3717,6 +3957,33 @@ ARMCore.prototype.compileArm = function(instruction) {
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op = this.armCompiler.constructSWI(immediate, condOp);
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op.writesPC = false;
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}
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// VCVT, VCVTR, VCVT
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// https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Instruction-Details/Alphabetical-list-of-instructions/VCVT--VCVTR--between-floating-point-and-integer--Floating-point-
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else if ((instruction & 0x0FB80E50) == 0x0EB80A40) {
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const cond = (instruction >> 28) & 0xf;
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const D = (instruction >> 22) & 0x1;
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const opc2 = (instruction >> 16) & 0x7;
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const Vd = (instruction >> 12) & 0xf;
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const sz = (instruction >> 8) & 0x1;
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const to_fixed = (instruction >> 7) & 0x1;
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const M = (instruction >> 5) & 0x1;
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const Vm = instruction & 0xf;
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op = this.armCompiler.constructVCVT(condOp, D, opc2, Vd, sz, to_fixed, M, Vm);
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op.writesPC = false;
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}
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// floating point vector instructions
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else {
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const cond = (instruction >> 28) & 0xf;
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const opcode = (instruction & 0x0F00000) >> 20;
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const CRn = (instruction & 0x000F0000) >> 16;
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const CRd = (instruction & 0x0000F000) >> 12;
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const CPn = (instruction & 0x00000F00) >> 8;
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const opcode2 = (instruction & 0b11100000) >> 5;
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const CRm = instruction & 0x0000000F;
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var condOp = this.conds[cond];
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op = this.armCompiler.constructVFP3Register(condOp, opcode, CRn, CRd, CPn, opcode2, CRm);
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op.writesPC = false;
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}
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break;
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default:
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throw new EmuHalt('Bad opcode: 0x' + instruction.toString(16));
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@ -4151,6 +4418,9 @@ export class ARM32CPU implements CPU, InstructionBased, ARMMMUInterface, ARMIRQI
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core : ARMCoreType;
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bus : ARMBus;
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memory : ARMMemoryRegion[];
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f64arr = new Float64Array(1);
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f32arr = new Float32Array(this.f64arr.buffer);
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i32arr = new Int32Array(this.f64arr.buffer);
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BASE_OFFSET = 24;
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OFFSET_MASK = 0x00FFFFFF;
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@ -200,7 +200,7 @@ export class ARM32Machine extends BasicScanlineMachine
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}
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getDebugCategories() {
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return ['CPU', 'Stack'];
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return ['CPU', 'Stack', 'FPU'];
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}
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getDebugInfo?(category: string, state: EmuState) : string {
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@ -241,6 +241,15 @@ export class ARM32Machine extends BasicScanlineMachine
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s += 'SPSR ' + hex(c.spsr,8) + '\n';
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s += 'cycl ' + c.cycles + '\n';
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return s;
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case 'FPU':
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var s = '';
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var c = state.c as ARMCoreState;
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for (var i=0; i<16; i++) {
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//let j = i+16;
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s += lpad('s'+i, 5) + ' ' + hex(c.ifprs[i],8) + ' ' + c.sfprs[i] + '\n';
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//s += lpad('s'+j, 5) + ' ' + lpad(c.sfprs[j]+'',8) + '\n';
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}
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return s;
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}
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}
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