From 48baf73ecbbc1ba4ef653653a895453923d27813 Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Tue, 21 Nov 2017 11:15:08 -0500 Subject: [PATCH] variable inspection, bitmaps for verilog, active high hsync/vsync, powerup vs reset --- presets/verilog/digits10.v | 10 ++- presets/verilog/hvsync_generator.v | 8 +-- src/pixed/pixeleditor.js | 6 +- src/platform/verilog.js | 98 ++++++++++++++++++++++++------ src/ui.js | 25 +++++++- 5 files changed, 112 insertions(+), 35 deletions(-) diff --git a/presets/verilog/digits10.v b/presets/verilog/digits10.v index e2500810..13013e0f 100644 --- a/presets/verilog/digits10.v +++ b/presets/verilog/digits10.v @@ -8,7 +8,7 @@ module digits10_case(digit, yofs, bits); wire [6:0] caseexpr = {digit,yofs}; always @(*) - case (caseexpr) + case (caseexpr)/*{w:5,h:5,count:10}*/ 7'o00: bits = 5'b11111; 7'o01: bits = 5'b10001; 7'o02: bits = 5'b10001; @@ -81,11 +81,9 @@ module digits10_array(digit, yofs, bits); reg [4:0] bitarray[10][5]; - always @(*) - bits = bitarray[digit][yofs]; - - initial - begin + assign bits = bitarray[digit][yofs]; + + initial begin/*{w:5,h:5,count:10}*/ bitarray[0][0] = 5'b11111; bitarray[0][1] = 5'b10001; bitarray[0][2] = 5'b10001; diff --git a/presets/verilog/hvsync_generator.v b/presets/verilog/hvsync_generator.v index 535df4cc..817961cb 100644 --- a/presets/verilog/hvsync_generator.v +++ b/presets/verilog/hvsync_generator.v @@ -43,11 +43,10 @@ module hvsync_generator( else vpos <= 0; - reg vga_HS, vga_VS; always @(posedge clk) begin - vga_HS <= (hpos>=START_H_RETRACE && hpos<=END_H_RETRACE); - vga_VS <= (vpos==START_V_RETRACE); + hsync <= (hpos>=START_H_RETRACE && hpos<=END_H_RETRACE); + vsync <= (vpos==START_V_RETRACE); end always @(posedge clk) @@ -55,9 +54,6 @@ module hvsync_generator( display_on <= (hpos>= 1; + } while (val != 0); + } + } + } + + function updateInspectionPostFrame() { + if (inspect_obj && inspect_sym) { + var ctx = video.getContext(); + var val = inspect_data[inspect_data.length-1]; + ctx.fillStyle = "black"; + ctx.fillRect(18, videoHeight-8, 30, 8); + ctx.fillStyle = "white"; + ctx.fillText(val.toString(10), 20, videoHeight-1); + } + } + function updateVideoFrame() { - var i=0; + var i=4; // TODO, start @ 0? + var trace=inspect_obj && inspect_sym; for (var y=0; y paddle_x ? 1 : 0; gen.vpaddle = y > paddle_y ? 1 : 0; for (var x=0; x= pos0) { + var l = editor.getLine(line); + var endsection; + if (platform_id == 'verilog') + endsection = l.indexOf('end') >= pos0; + else + endsection = l.indexOf(';') >= pos0; + if (endsection) { var end = {line:line, ch:editor.getLine(line).length}; return {obj:obj, start:start, end:end}; }