diff --git a/package.json b/package.json
index 40baa8ff..b44c9608 100644
--- a/package.json
+++ b/package.json
@@ -21,8 +21,8 @@
   "scripts": {
     "build": "tsc",
     "test": "npm run test-node && npm run test-browser",
-    "test-one": "mocha --recursive --timeout 20000",
-    "test-node": "mocha --recursive --timeout 20000 test/cli",
+    "test-one": "mocha --recursive --timeout 30000",
+    "test-node": "mocha --recursive --timeout 30000 test/cli",
     "test-profile": "mocha --recursive --timeout 60000 --prof test/cli",
     "test-browser": "mocha-phantomjs ./testemu.html"
   },
diff --git a/presets/apple2/hgrtest.a b/presets/apple2/hgrtest.a
new file mode 100644
index 00000000..5bc43719
--- /dev/null
+++ b/presets/apple2/hgrtest.a
@@ -0,0 +1,22 @@
+	processor 6502
+	seg program
+	org $803
+
+.start
+	sta $c050	; set graphics
+        sta $c052	; no mixed mode
+	sta $c057	; set hires
+        
+        ldx #0
+.loop   inc $2000,x	; increment hgr byte
+        inx
+        bne .loop
+        lda .loop+2	; increment hi byte of instruction
+        clc
+        adc #1
+        sta .loop+2
+        cmp #$40
+        bne .loop
+        lda #$20	; reset to $2000
+        sta .loop+2
+	jmp .start
diff --git a/presets/apple2/siegegame.c b/presets/apple2/siegegame.c
index 3d5a4fbe..bf10edb7 100644
--- a/presets/apple2/siegegame.c
+++ b/presets/apple2/siegegame.c
@@ -115,13 +115,16 @@ void move_player(Player* p) {
 
 void human_control(Player* p) {
   byte dir = 0xff;
-  byte joy;
+  byte key;
   if (!p->human) return;
-  joy = joy_read (JOY_1);
-  if (joy & JOY_LEFT_MASK) dir = D_LEFT;
-  if (joy & JOY_RIGHT_MASK) dir = D_RIGHT;
-  if (joy & JOY_UP_MASK) dir = D_UP;
-  if (joy & JOY_DOWN_MASK) dir = D_DOWN;
+  if (!kbhit()) return;
+  key = cgetc();
+  switch (key) {
+    case 'i': dir = D_UP; break;
+    case 'j': dir = D_LEFT; break;
+    case 'k': dir = D_RIGHT; break;
+    case 'm': dir = D_DOWN; break;
+  }
   // don't let the player reverse
   if (dir < 0x80 && dir != (p->dir ^ 2)) {
     p->dir = dir;
diff --git a/presets/vcs/examples/score6.a b/presets/vcs/examples/score6.a
index 232d9d9d..81daf065 100644
--- a/presets/vcs/examples/score6.a
+++ b/presets/vcs/examples/score6.a
@@ -64,9 +64,9 @@ NextFrame
         TIMER_WAIT
 
 	TIMER_SETUP 30
-        lda #1
-        ldx #0
-        ldy #0
+        lda #$01
+        ldx #$00
+        ldy #$00
         jsr AddScore
         TIMER_WAIT
         jmp NextFrame
diff --git a/presets/verilog/ball_paddle.v b/presets/verilog/ball_paddle.v
index a269268d..668fec3f 100644
--- a/presets/verilog/ball_paddle.v
+++ b/presets/verilog/ball_paddle.v
@@ -21,7 +21,7 @@ module ball_paddle_top(clk, reset, hpaddle, hsync, vsync, rgb);
   reg ball_speed_x;
   reg ball_dir_y;
   
-  reg brick_array [0:BRICKS_H * BRICKS_V];
+  reg brick_array [0:BRICKS_H*BRICKS_V-1]; // 16*8 = 128 bits
 
   wire [3:0] score0;
   wire [3:0] score1;
diff --git a/presets/verilog/paddles.v b/presets/verilog/paddles.v
index 0920b3b4..cbdd1b90 100644
--- a/presets/verilog/paddles.v
+++ b/presets/verilog/paddles.v
@@ -1,6 +1,6 @@
 `include "hvsync_generator.v"
 
-module top(clk, reset, hsync, vsync, hpaddle, vpaddle, rgb);
+module paddles_top(clk, reset, hsync, vsync, hpaddle, vpaddle, rgb);
 
   input clk, reset;
   input hpaddle, vpaddle;
diff --git a/presets/verilog/racing_game.v b/presets/verilog/racing_game.v
index 15b86362..98c66683 100644
--- a/presets/verilog/racing_game.v
+++ b/presets/verilog/racing_game.v
@@ -2,7 +2,7 @@
 `include "sprite_bitmap.v"
 `include "sprite_renderer.v"
 
-module sprite_multiple_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
+module racing_game_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
 
   input clk;
   input hpaddle, vpaddle;
diff --git a/presets/verilog/ram.v b/presets/verilog/ram.v
index 667aee00..7e4a789b 100644
--- a/presets/verilog/ram.v
+++ b/presets/verilog/ram.v
@@ -46,4 +46,25 @@ module RAM_async(clk, addr, din, dout, we);
 
 endmodule
 
+module RAM_async_tristate(clk, addr, data, we);
+  
+  parameter A = 10; // # of address bits
+  parameter D = 8;  // # of data bits
+  
+  input  clk;		// clock
+  input  [A-1:0] addr;	// address
+  inout  [D-1:0] data;	// data in/out
+  input  we;		// write enable
+  
+  reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
+  
+  always @(posedge clk) begin
+    if (we)		 // if write enabled
+      mem[addr] <= data; // write memory from data
+  end
+
+  assign data = !we ? mem[addr] : {D{1'bz}}; // read memory to data (async)
+
+endmodule
+
 `endif
diff --git a/presets/verilog/sprite_renderer.v b/presets/verilog/sprite_renderer.v
index 1e2a6d5c..b90c1e63 100644
--- a/presets/verilog/sprite_renderer.v
+++ b/presets/verilog/sprite_renderer.v
@@ -86,7 +86,7 @@ module sprite_renderer(clk, vstart, load, hstart, rom_addr, rom_bits,
 endmodule
 
 
-module test_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
+module sprite_render_test_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
 
   input clk;
   input hpaddle, vpaddle;
diff --git a/src/platform/verilog.js b/src/platform/verilog.js
index 5674c6c9..c4145b84 100644
--- a/src/platform/verilog.js
+++ b/src/platform/verilog.js
@@ -601,6 +601,7 @@ var VerilogPlatform = function(mainElement, options) {
       // compile Verilog code
       var base = new VerilatorBase();
       gen = new mod(base);
+      //$.extend(gen, base);
       gen.__proto__ = base;
       current_output = output;
       module_name = output.name ? output.name.substr(1) : "top";
diff --git a/src/project.ts b/src/project.ts
index c796bc19..ee9b1b24 100644
--- a/src/project.ts
+++ b/src/project.ts
@@ -183,7 +183,7 @@ export class CodeProject {
         // TODO: should get rid of this msg format
         this.worker.postMessage({
           code:text,
-          path:this.mainpath,
+          path:getFilenameForPath(this.mainpath),
           dependencies:depends,
           platform:this.platform_id,
           tool:this.platform.getToolForFilename(this.mainpath)