mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2025-01-02 23:30:21 +00:00
support `include statements in verilog; book link changes; paddle/switches; scope transitions
This commit is contained in:
Steven Hugg
parent
4256ee7bc2
commit
4f73cde7cc
@ -100,6 +100,10 @@ div.mem_info {
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}
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.btn_group.view_group {
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}
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.btn_active {
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border-radius:3px;
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color: #ffffff;
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}
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.seg_code { color: #ff9966; }
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.seg_data { color: #66ff66; }
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.seg_stack { color: #ffff66; }
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@ -110,14 +110,14 @@ body {
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<a target="_new" href="https://www.amazon.com/gp/product/1541021304/ref=as_li_qf_sp_asin_il_tl?ie=UTF8&tag=pzp-20&camp=1789&creative=9325&linkCode=as2&creativeASIN=B01N4DSRIZ&linkId=04d39e274c06e6c93b93d20a9a977111">
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<img src="images/book_a2600.jpg" style="float:right"/></a>
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Want to learn more?<br>
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Get the book<br>
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Get the book:<br>
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<a target="_new" href="https://www.amazon.com/gp/product/1541021304/ref=as_li_qf_sp_asin_il_tl?ie=UTF8&tag=pzp-20&camp=1789&creative=9325&linkCode=as2&creativeASIN=B01N4DSRIZ&linkId=04d39e274c06e6c93b93d20a9a977111">
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Making Games For The Atari 2600</a>
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</div>
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<div class="booklink" id="booklink_arcade">
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<a target="_new" href="https://www.amazon.com/gp/product/B0713RQL8X/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=B0713RQL8X&linkCode=as2&tag=pzp-20&linkId=e8e05e34acf1b54d81aced148a67790c">
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<img height="72em" src="images/book_arcade.jpg" style="float:right"/></a>
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New book!<br>
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Get the book:<br>
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<a target="_new" href="https://www.amazon.com/Making-8-bit-Arcade-Games-C/dp/1545484759">
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Making 8-bit Arcade Games in C</a>
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</div>
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38
presets/verilog/clock_divider.v
Normal file
38
presets/verilog/clock_divider.v
Normal file
@ -0,0 +1,38 @@
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module clock_divider(
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input clk,
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output reg clk_div2,
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output reg clk_div4,
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output reg clk_div8,
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output reg clk_div16,
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output reg [3:0] counter,
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output cntr_div2,
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output cntr_div4,
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output cntr_div8,
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output cntr_div16
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);
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// simple ripple clock divider
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always @(posedge clk)
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clk_div2 <= ~clk_div2;
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always @(posedge clk_div2)
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clk_div4 <= ~clk_div4;
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always @(posedge clk_div4)
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clk_div8 <= ~clk_div8;
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always @(posedge clk_div8)
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clk_div16 <= ~clk_div16;
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// use bits of (4-bit) counter to divide clocks
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always @(posedge clk)
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counter <= counter + 1;
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assign cntr_div2 = counter[0];
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assign cntr_div4 = counter[1];
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assign cntr_div8 = counter[2];
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assign cntr_div16 = counter[3];
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endmodule
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@ -1,13 +1,12 @@
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module hvsync(
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clk, hsync, vsync, inDisplayArea, CounterX, CounterY, pixel);
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module hvsync_generator(
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clk, hsync, vsync, inDisplayArea, CounterX, CounterY);
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input clk;
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output hsync, vsync;
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output inDisplayArea;
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output [8:0] CounterX;
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output [8:0] CounterY;
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output pixel;
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// constant declarations for VGA sync parameters
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localparam H_DISPLAY = 256; // horizontal display area
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@ -28,11 +27,10 @@ module hvsync(
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reg [8:0] CounterX;
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reg [8:0] CounterY;
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reg pixel;
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wire CounterXmaxed = (CounterX==H_MAX);
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wire CounterYmaxed = (CounterY==V_MAX);
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always @(posedge clk)
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always @(posedge clk)
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if(CounterXmaxed)
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CounterX <= 0;
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else
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@ -56,8 +54,6 @@ module hvsync(
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always @(posedge clk)
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begin
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inDisplayArea <= (CounterX<H_DISPLAY) && (CounterY<V_DISPLAY);
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pixel <= inDisplayArea &&
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(((CounterX&7)==0) || ((CounterY&7)==0));
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end
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assign hsync = ~vga_HS;
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19
presets/verilog/lfsr.v
Normal file
19
presets/verilog/lfsr.v
Normal file
@ -0,0 +1,19 @@
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module LFSR8_11D(
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input clk,
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output reg [7:0] LFSR = 255 // put here the initial value
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);
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wire feedback = LFSR[7];
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always @(posedge clk)
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begin
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LFSR[0] <= feedback;
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LFSR[1] <= LFSR[0];
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LFSR[2] <= LFSR[1] ^ feedback;
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LFSR[3] <= LFSR[2] ^ feedback;
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LFSR[4] <= LFSR[3] ^ feedback;
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LFSR[5] <= LFSR[4];
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LFSR[6] <= LFSR[5];
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LFSR[7] <= LFSR[6];
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end
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endmodule
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3623
presets/verilog/pong.v
Normal file
3623
presets/verilog/pong.v
Normal file
File diff suppressed because it is too large
Load Diff
27
presets/verilog/test_hvsync.v
Normal file
27
presets/verilog/test_hvsync.v
Normal file
@ -0,0 +1,27 @@
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`include "hvsync_generator.v"
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module test_hvsync_top(clk, hsync, vsync, rgb);
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input clk;
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output hsync, vsync;
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output [2:0] rgb;
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wire inDisplayArea;
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wire [8:0] CounterX;
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wire [8:0] CounterY;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.hsync(hsync),
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.vsync(vsync),
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.inDisplayArea(inDisplayArea),
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.CounterX(CounterX),
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.CounterY(CounterY)
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);
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wire r = inDisplayArea &&
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(((CounterX&7)==0) || ((CounterY&7)==0));
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wire g = inDisplayArea && CounterY[4];
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wire b = inDisplayArea && CounterX[4];
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assign rgb = {b,g,r};
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endmodule
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@ -411,7 +411,7 @@ var SampleAudio = function(clockfreq) {
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if (sfrac >= 1) {
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sfrac -= 1;
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accum = 0;
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this.feedSingleSample(accum / sfrac);
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this.addSingleSample(accum / sfrac);
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}
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}
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}
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@ -1,10 +1,27 @@
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"use strict";
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var VERILOG_PRESETS = [
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{id:'hvsync.v', name:'Hello Verilog'},
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{id:'clock_divider.v', name:'Clock Divider'},
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{id:'hvsync_generator.v', name:'Video Sync Generator'},
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{id:'test_hvsync.v', name:'Test Pattern'},
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{id:'lfsr.v', name:'Linear Feedback Shift Register'},
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{id:'pong.v', name:'Pong'},
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];
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var VERILOG_KEYCODE_MAP = makeKeycodeMap([
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[Keys.VK_LEFT, 0, 0x1],
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[Keys.VK_RIGHT, 0, 0x2],
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[Keys.VK_UP, 0, 0x4],
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[Keys.VK_DOWN, 0, 0x8],
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[Keys.VK_SPACE, 0, 0x10],
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[Keys.VK_SHIFT, 0, 0x20],
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[Keys.VK_1, 0, 0x40],
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[Keys.VK_2, 0, 0x80],
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[Keys.VK_5, 0, 0x100],
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[Keys.VK_6, 0, 0x200],
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[Keys.VK_7, 0, 0x400],
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]);
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function VerilatorBase() {
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this.VL_RAND_RESET_I = function(bits) { return Math.floor(Math.random() * (1<<bits)); }
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@ -71,21 +88,19 @@ function VerilatorBase() {
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var VerilogPlatform = function(mainElement, options) {
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var self = this;
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var video, audio;
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var videoWidth=288;
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var videoHeight=248;
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var videoWidth = 288;
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var videoHeight = 248;
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var idata, timer;
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var gen;
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var frameRate = 60;
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var AUDIO_FREQ = 15700;
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var AUDIO_FREQ = 15750;
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var current_output;
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var paddle_x = 0;
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var paddle_y = 0;
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var switches = [0];
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this.getPresets = function() { return VERILOG_PRESETS; }
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function tick2() {
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gen.tick2();
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audio.addSingleSample(0+gen.audio); // TODO: sync with audio freq
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}
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var RGBLOOKUP = [
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0xff111111,
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0xff1111ff,
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@ -97,24 +112,32 @@ var VerilogPlatform = function(mainElement, options) {
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0xffffffff,
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];
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function vidtick() {
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gen.tick2();
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audio.addSingleSample(0+gen.spkr); // TODO: sync with audio freq
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}
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function updateVideoFrame() {
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var i=0;
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for (var y=0; y<videoHeight; y++) {
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gen.hpaddle = y > paddle_x ? 1 : 0;
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gen.vpaddle = y > paddle_y ? 1 : 0;
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for (var x=0; x<videoWidth; x++) {
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tick2();
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vidtick();
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idata[i++] = RGBLOOKUP[gen.rgb];
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}
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var z=0;
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while (gen.hsync && z++<videoWidth) tick2();
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while (!gen.hsync && z++<videoWidth) tick2();
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while (gen.hsync && z++<videoWidth) vidtick();
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while (!gen.hsync && z++<videoWidth) vidtick();
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}
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var z=0;
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while (gen.vsync && z++<videoWidth*80) tick2();
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while (!gen.vsync && z++<videoWidth*80) tick2();
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while (gen.vsync && z++<videoWidth*80) vidtick();
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while (!gen.vsync && z++<videoWidth*80) vidtick();
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video.updateFrame();
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}
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var yposlist = [];
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var lasty = [];
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function updateScopeFrame() {
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var arr = current_output.ports;
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@ -125,6 +148,7 @@ var VerilogPlatform = function(mainElement, options) {
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}
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var COLOR_SIGNAL = 0xff11ff11;
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var COLOR_BORDER = 0xff661111;
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var COLOR_TRANS_SIGNAL = 0xff116611;
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for (var x=0; x<videoWidth; x++) {
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gen.clk ^= 1;
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gen.eval();
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@ -137,11 +161,19 @@ var VerilogPlatform = function(mainElement, options) {
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var ys = hi>1 ? v.len*2+8 : 8;
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var y2 = y1+ys;
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var z = gen[v.name];
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var y = y2 - ys*((z-lo)/hi);
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var y = Math.round(y2 - ys*((z-lo)/hi));
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yposlist[i] = y2;
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var ly = lasty[i];
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if (x > 0 && ly != y) {
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var dir = ly < y ? 1 : -1;
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while ((ly += dir) != y && ly >= y1 && ly <= y2) {
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idata[x + ly*videoWidth] = COLOR_TRANS_SIGNAL;
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}
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}
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lasty[i] = y;
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//idata[x + y1*videoWidth] = COLOR_BORDER;
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//idata[x + y2*videoWidth] = COLOR_BORDER;
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idata[x + Math.round(y)*videoWidth] = COLOR_SIGNAL;
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idata[x + y*videoWidth] = COLOR_SIGNAL;
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y1 += ys+yb;
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}
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}
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@ -152,7 +184,10 @@ var VerilogPlatform = function(mainElement, options) {
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ctx.fillStyle = "white";
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for (var i=0; i<arr.length; i++) {
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var v = arr[i];
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ctx.textAlign = 'left';
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ctx.fillText(v.name, 1, yposlist[i]);
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//ctx.textAlign = 'right';
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//ctx.fillText(""+gen[v.name], videoWidth-1, yposlist[i]);
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}
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}
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@ -160,12 +195,18 @@ var VerilogPlatform = function(mainElement, options) {
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// TODO
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video = new RasterVideo(mainElement,videoWidth,videoHeight);
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video.create();
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setKeyboardFromMap(video, switches, VERILOG_KEYCODE_MAP);
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$(video.canvas).mousemove(function(e) {
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paddle_x = Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width());
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paddle_y = Math.floor(e.offsetY * video.canvas.height / $(video.canvas).height() - 20);
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});
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audio = new SampleAudio(AUDIO_FREQ);
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idata = video.getFrameData();
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// TODO: 15.7 kHz?
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timer = new AnimationTimer(frameRate, function() {
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if (!self.isRunning())
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return;
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gen.switches = switches[0];
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if (gen.vsync !== undefined && gen.hsync !== undefined && gen.rgb !== undefined)
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updateVideoFrame();
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else
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@ -173,8 +214,27 @@ var VerilogPlatform = function(mainElement, options) {
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});
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}
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function printErrorCodeContext(e, code) {
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if (e.lineNumber && e.message) {
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var lines = code.split('\n');
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var s = e.message + '\n';
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for (var i=0; i<lines.length; i++) {
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if (i > e.lineNumber-5 && i < e.lineNumber+5) {
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s += lines[i] + '\n';
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}
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}
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console.log(s);
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}
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}
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this.loadROM = function(title, output) {
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var mod = new Function('base', output.code);
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var mod;
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try {
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mod = new Function('base', output.code);
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} catch (e) {
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printErrorCodeContext(e, output.code);
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throw e;
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}
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var base = new VerilatorBase();
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gen = new mod(base);
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gen.__proto__ = base;
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32
src/ui.js
32
src/ui.js
@ -208,7 +208,9 @@ function setLastPreset(id) {
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}
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function updatePreset(current_preset_id, text) {
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if (text.trim().length && (originalFileID != current_preset_id || text != originalText)) {
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// TODO: do we have to save all Verilog thingies?
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if (text.trim().length &&
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(originalFileID != current_preset_id || text != originalText || platform_id=='verilog')) {
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store.saveFile(current_preset_id, text);
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}
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}
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@ -389,11 +391,30 @@ function updateSelector() {
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});
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}
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function loadFileDependencies(text) {
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var arr = [];
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if (platform_id == 'verilog') {
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var re = /`include\s+"(.+)"/g;
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var m;
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while (m = re.exec(text)) {
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arr.push({
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filename:m[1],
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text:store.loadFile(m[1]) // TODO: if missing?
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});
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}
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}
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return arr;
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}
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function setCode(text) {
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if (pendingWorkerMessages++ > 0)
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return;
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worker.postMessage({code:text, platform:platform_id,
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tool:platform.getToolForFilename(current_preset_id)});
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worker.postMessage({
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code:text,
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dependencies:loadFileDependencies(text),
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platform:platform_id,
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tool:platform.getToolForFilename(current_preset_id)
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});
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toolbar.addClass("is-busy");
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$('#compile_spinner').css('visibility', 'visible');
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}
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@ -437,7 +458,8 @@ function setCompileOutput(data) {
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div.appendChild(document.createTextNode("\u24cd"));
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var tooltip = document.createElement("span");
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tooltip.setAttribute("class", "tooltiptext");
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if (lines2errmsg[line]) msg = lines2errmsg[line] + "\n" + msg;
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if (lines2errmsg[line])
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msg = lines2errmsg[line] + "\n" + msg;
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tooltip.appendChild(document.createTextNode(msg));
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lines2errmsg[line] = msg;
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div.appendChild(tooltip);
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@ -1257,7 +1279,7 @@ function initPlatform() {
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function showBookLink() {
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if (platform_id == 'vcs')
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$("#booklink_vcs").show();
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else
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else if (platform_id == 'mw8080bw' || platform_id == 'vicdual' || platform_id == 'galaxian-scramble' || platform_id == 'vector-z80color' || platform_id == 'williams-z80')
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$("#booklink_arcade").show();
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}
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@ -12,6 +12,17 @@ function parseDecls(text, arr, name, bin, bout) {
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ofs:parseInt(m[4]),
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});
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}
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re = new RegExp(name + "(\\d+)[(](\\w+)\\[(\\d+)\\],(\\d+),(\\d+)[)]", 'gm');
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var m;
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while ((m = re.exec(text))) {
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arr.push({
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wordlen:parseInt(m[1]),
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name:m[2],
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arrlen:parseInt(m[3]),
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len:parseInt(m[4]),
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ofs:parseInt(m[5]),
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});
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}
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}
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function buildModule(o) {
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@ -22,7 +33,10 @@ function buildModule(o) {
|
||||
m += "\tself." + o.ports[i].name + ";\n";
|
||||
}
|
||||
for (var i=0; i<o.signals.length; i++) {
|
||||
m += "\tself." + o.signals[i].name + ";\n";
|
||||
if (o.signals[i].arrlen)
|
||||
m += "\tvar " + o.signals[i].name + " = self." + o.signals[i].name + " = [];\n";
|
||||
else
|
||||
m += "\tself." + o.signals[i].name + ";\n";
|
||||
}
|
||||
for (var i=0; i<o.funcs.length; i++) {
|
||||
m += o.funcs[i];
|
||||
@ -44,7 +58,9 @@ function translateFunction(text) {
|
||||
text = text.replace(/\b([0-9]+)U/gi, '$1');
|
||||
text = text.replace(/\bQData /, 'var ');
|
||||
text = text.replace(/\bbool /, '');
|
||||
text = text.replace(/\bint /, 'var ');
|
||||
text = text.replace(/(\w+ = VL_RAND_RESET_I)/g, 'self.$1');
|
||||
//text = text.replace(/(\w+\[\w+\] = VL_RAND_RESET_I)/g, 'self.$1');
|
||||
text = text.replace(/^#/gm, '//#');
|
||||
text = text.replace(/VL_LIKELY/g, '!!');
|
||||
text = text.replace(/VL_UNLIKELY/g, '!!');
|
||||
|
||||
@ -530,7 +530,7 @@ function parseCA65Listing(code, mapfile) {
|
||||
return {lines:lines, errors:errors};
|
||||
}
|
||||
|
||||
function assemblelinkCA65(code, platform, warnings) {
|
||||
function assemblelinkCA65(code, platform) {
|
||||
var params = PLATFORM_PARAMS[platform];
|
||||
if (!params) throw Error("Platform not supported: " + platform);
|
||||
var errors = "";
|
||||
@ -871,14 +871,6 @@ function compileSDCC(code, platform) {
|
||||
starttime();
|
||||
SDCC.callMain(args);
|
||||
endtime("compile");
|
||||
/*
|
||||
// ignore if all are warnings (TODO?)
|
||||
var nwarnings = 0;
|
||||
for (var err of msvc_errors) {
|
||||
if (err.type && err.type.startsWith("warning"))
|
||||
nwarnings++;
|
||||
}
|
||||
*/
|
||||
// TODO: preprocessor errors w/ correct file
|
||||
if (msvc_errors.length /* && nwarnings < msvc_errors.length*/) {
|
||||
return {errors:msvc_errors};
|
||||
@ -901,7 +893,6 @@ function compileSDCC(code, platform) {
|
||||
result.asmlines = result.lines;
|
||||
result.lines = result.srclines;
|
||||
result.srclines = null;
|
||||
//result.errors = result.errors.concat(warnings);
|
||||
return result;
|
||||
}
|
||||
|
||||
@ -1036,11 +1027,21 @@ function detectModuleName(code) {
|
||||
return m ? m[1] : null;
|
||||
}
|
||||
|
||||
function compileVerilator(code, platform) {
|
||||
function writeDependencies(depends, FS, errors) {
|
||||
if (depends) {
|
||||
for (var i=0; i<depends.length; i++) {
|
||||
var d = depends[i];
|
||||
if (d.text)
|
||||
FS.writeFile(d.filename, d.text, {encoding:'utf8'});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
function compileVerilator(code, platform, options) {
|
||||
loadWASM("verilator_bin");
|
||||
load("verilator2js");
|
||||
var errors = [];
|
||||
var match_fn = makeErrorMatcher(errors, /%Error: (.+?:)?(\d+)?[:]?\s*(.+)/, 2, 3);
|
||||
var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?:)?(\d+)?[:]?\s*(.+)/i, 3, 4);
|
||||
var verilator_mod = verilator_bin({
|
||||
wasmBinary:wasmBlob['verilator_bin'],
|
||||
noInitialRun:true,
|
||||
@ -1055,6 +1056,7 @@ function compileVerilator(code, platform) {
|
||||
var FS = verilator_mod['FS'];
|
||||
//setupFS(FS);
|
||||
FS.writeFile(topmod+".v", code);
|
||||
writeDependencies(options.dependencies, FS, errors);
|
||||
starttime();
|
||||
verilator_mod.callMain(["--cc", "-O3", "--top-module", topmod, topmod+".v"]);
|
||||
endtime("compile");
|
||||
@ -1106,7 +1108,8 @@ onmessage = function(e) {
|
||||
var platform = e.data.platform;
|
||||
var toolfn = TOOLS[e.data.tool];
|
||||
if (!toolfn) throw "no tool named " + e.data.tool;
|
||||
var result = toolfn(code, platform);
|
||||
var dependencies = e.data.dependencies;
|
||||
var result = toolfn(code, platform, e.data);
|
||||
result.params = PLATFORM_PARAMS[platform];
|
||||
if (result) {
|
||||
postMessage(result);
|
||||
|
||||
@ -105,7 +105,7 @@ describe('Worker', function() {
|
||||
compile('plasm', 'word x = ', 'apple2', done, 0, 0, 1);
|
||||
});
|
||||
it('should compile CC65', function(done) {
|
||||
compile('cc65', 'int main() {\nint x=1;\nreturn x+2;\n}', 'nes-conio', done, 2947, 4);
|
||||
compile('cc65', 'int main() {\nint x=1;\nreturn x+2;\n}', 'nes-conio', done, 40976, 3);
|
||||
});
|
||||
it('should NOT compile CC65', function(done) {
|
||||
compile('cc65', 'int main() {\nint x=1;\nprintf("%d",x);\nreturn x+2;\n}', 'nes-conio', done, 0, 0, 1);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user