From 5cf56f9d04705d70dace4764798a46d9299a2265 Mon Sep 17 00:00:00 2001 From: Steven Hugg Date: Tue, 6 Jul 2021 15:45:27 -0500 Subject: [PATCH] verilog: sort var defs, fix video sync --- src/common/hdl/fuzz.ts | 17 +- src/common/hdl/hdlruntime.ts | 32 ++- src/common/hdl/hdlwasm.ts | 123 +++++---- src/common/hdl/vxmlparser.ts | 15 +- src/common/hdl/vxmltest.ts | 4 +- src/platform/verilog.ts | 14 +- test/cli/testverilog.js | 113 +++----- test/cli/verilog/t_alw_nosplit.v | 132 +++++++++ test/cli/verilog/t_alw_reorder.v | 56 ++++ test/cli/verilog/t_alw_split_rst.v | 159 +++++++++++ test/cli/verilog/t_assert_basic.v | 50 ++++ test/cli/verilog/t_assert_casez.v | 30 +++ test/cli/verilog/t_assert_comp.v | 19 ++ test/cli/verilog/t_assert_cover.v | 158 +++++++++++ test/cli/verilog/t_assert_disable_iff.v | 82 ++++++ test/cli/verilog/t_assert_elab.v | 26 ++ test/cli/verilog/t_assert_implication.v | 130 +++++++++ test/cli/verilog/t_assert_on.v | 19 ++ test/cli/verilog/t_assert_property.v | 58 ++++ test/cli/verilog/t_assert_question.v | 34 +++ test/cli/verilog/t_assert_synth.v | 114 ++++++++ test/cli/verilog/t_assign_inline.v | 53 ++++ test/cli/verilog/t_attr_parenstar.v | 42 +++ test/cli/verilog/t_bitsel_enum.v | 28 ++ test/cli/verilog/t_bitsel_slice.v | 83 ++++++ test/cli/verilog/t_blocking.v | 96 +++++++ test/cli/verilog/t_case_deep.v | 343 ++++++++++++++++++++++++ test/cli/verilog/t_case_dupitems.v | 81 ++++++ test/cli/verilog/t_case_group.v | 26 ++ test/cli/verilog/t_case_itemwidth.v | 124 +++++++++ test/cli/verilog/t_case_onehot.v | 96 +++++++ test/cli/verilog/t_case_orig.v | 187 +++++++++++++ test/cli/verilog/t_case_reducer.v | 279 +++++++++++++++++++ test/cli/verilog/t_case_x.v | 66 +++++ test/cli/verilog/t_cellarray.v | 99 +++++++ test/cli/verilog/t_chg_first.v | 72 +++++ test/cli/verilog/t_clk_gate_ext.v | 25 ++ test/cli/verilog/t_clk_gater.v | 160 ----------- test/cli/verilog/t_clk_vecgen1.v | 124 --------- test/cli/verilog/t_clocker.v | 64 +++++ test/cli/verilog/t_concat_large.v | 20 ++ test/cli/verilog/t_concat_opt.v | 71 +++++ test/cli/verilog/t_concat_sel.v | 74 +++++ test/cli/verilog/t_const.v | 22 ++ test/cli/verilog/t_crazy_sel.v | 43 +++ test/cli/verilog/t_dynarray_param.v | 54 ++++ test/cli/verilog/t_fork_bbox.v | 18 ++ test/cli/verilog/t_fork_label.v | 34 +++ test/cli/verilog/t_func_endian.v | 99 +++++++ test/cli/verilog/t_func_first.v | 39 +++ test/cli/verilog/t_func_flip.v | 54 ++++ test/cli/verilog/t_func_gen.v | 34 +++ test/cli/verilog/t_func_grey.v | 72 +++++ test/cli/verilog/t_func_lib.v | 12 + test/cli/verilog/t_func_mlog2.v | 56 ++++ test/cli/verilog/t_func_numones.v | 50 ++++ test/cli/verilog/t_func_outfirst.v | 116 ++++++++ test/cli/verilog/t_func_outp.v | 94 +++++++ test/cli/verilog/t_func_paramed.v | 80 ++++++ test/cli/verilog/t_func_plog.v | 103 +++++++ test/cli/verilog/t_func_range.v | 64 +++++ test/cli/verilog/t_func_real_param.v | 28 ++ test/cli/verilog/t_func_regfirst.v | 78 ++++++ test/cli/verilog/t_func_under.v | 27 ++ test/cli/verilog/t_func_under2.v | 45 ++++ test/cli/verilog/t_func_uninit.v | 33 +++ test/cli/verilog/t_func_wide.v | 45 ++++ 67 files changed, 4473 insertions(+), 425 deletions(-) create mode 100644 test/cli/verilog/t_alw_nosplit.v create mode 100644 test/cli/verilog/t_alw_reorder.v create mode 100644 test/cli/verilog/t_alw_split_rst.v create mode 100644 test/cli/verilog/t_assert_basic.v create mode 100644 test/cli/verilog/t_assert_casez.v create mode 100644 test/cli/verilog/t_assert_comp.v create mode 100644 test/cli/verilog/t_assert_cover.v create mode 100644 test/cli/verilog/t_assert_disable_iff.v create mode 100644 test/cli/verilog/t_assert_elab.v create mode 100644 test/cli/verilog/t_assert_implication.v create mode 100644 test/cli/verilog/t_assert_on.v create mode 100644 test/cli/verilog/t_assert_property.v create mode 100644 test/cli/verilog/t_assert_question.v create mode 100644 test/cli/verilog/t_assert_synth.v create mode 100644 test/cli/verilog/t_assign_inline.v create mode 100644 test/cli/verilog/t_attr_parenstar.v create mode 100644 test/cli/verilog/t_bitsel_enum.v create mode 100644 test/cli/verilog/t_bitsel_slice.v create mode 100644 test/cli/verilog/t_blocking.v create mode 100644 test/cli/verilog/t_case_deep.v create mode 100644 test/cli/verilog/t_case_dupitems.v create mode 100644 test/cli/verilog/t_case_group.v create mode 100644 test/cli/verilog/t_case_itemwidth.v create mode 100644 test/cli/verilog/t_case_onehot.v create mode 100644 test/cli/verilog/t_case_orig.v create mode 100644 test/cli/verilog/t_case_reducer.v create mode 100644 test/cli/verilog/t_case_x.v create mode 100644 test/cli/verilog/t_cellarray.v create mode 100644 test/cli/verilog/t_chg_first.v create mode 100644 test/cli/verilog/t_clk_gate_ext.v delete mode 100644 test/cli/verilog/t_clk_gater.v delete mode 100644 test/cli/verilog/t_clk_vecgen1.v create mode 100644 test/cli/verilog/t_clocker.v create mode 100644 test/cli/verilog/t_concat_large.v create mode 100644 test/cli/verilog/t_concat_opt.v create mode 100644 test/cli/verilog/t_concat_sel.v create mode 100644 test/cli/verilog/t_const.v create mode 100644 test/cli/verilog/t_crazy_sel.v create mode 100644 test/cli/verilog/t_dynarray_param.v create mode 100644 test/cli/verilog/t_fork_bbox.v create mode 100644 test/cli/verilog/t_fork_label.v create mode 100644 test/cli/verilog/t_func_endian.v create mode 100644 test/cli/verilog/t_func_first.v create mode 100644 test/cli/verilog/t_func_flip.v create mode 100644 test/cli/verilog/t_func_gen.v create mode 100644 test/cli/verilog/t_func_grey.v create mode 100644 test/cli/verilog/t_func_lib.v create mode 100644 test/cli/verilog/t_func_mlog2.v create mode 100644 test/cli/verilog/t_func_numones.v create mode 100644 test/cli/verilog/t_func_outfirst.v create mode 100644 test/cli/verilog/t_func_outp.v create mode 100644 test/cli/verilog/t_func_paramed.v create mode 100644 test/cli/verilog/t_func_plog.v create mode 100644 test/cli/verilog/t_func_range.v create mode 100644 test/cli/verilog/t_func_real_param.v create mode 100644 test/cli/verilog/t_func_regfirst.v create mode 100644 test/cli/verilog/t_func_under.v create mode 100644 test/cli/verilog/t_func_under2.v create mode 100644 test/cli/verilog/t_func_uninit.v create mode 100644 test/cli/verilog/t_func_wide.v diff --git a/src/common/hdl/fuzz.ts b/src/common/hdl/fuzz.ts index 4687f3b9..d6c666e1 100644 --- a/src/common/hdl/fuzz.ts +++ b/src/common/hdl/fuzz.ts @@ -1,6 +1,7 @@ //import binaryen = require('binaryen'); -import { HDLModuleJS } from "./hdlruntime"; +import { fn } from "jquery"; +import { HDLError, HDLModuleJS } from "./hdlruntime"; import { HDLModuleWASM } from "./hdlwasm"; import { CompileError, VerilogXMLParser } from "./vxmlparser"; @@ -28,8 +29,16 @@ export function fuzz(buf) { if (1) { var jmod = new HDLModuleJS(parser.modules['TOP'], parser.modules['@CONST-POOL@']); jmod.init(); - jmod.powercycle(); - jmod.tick2(10000); - jmod.dispose(); + try { + jmod.powercycle(); + jmod.tick2(10000); + } catch (e) { + if (e instanceof HDLError) return; + const fs = require('fs'); + fs.writeFileSync('hdlfuzz-output.js', jmod.getJSCode()); + throw e; + } finally { + jmod.dispose(); + } } } diff --git a/src/common/hdl/hdlruntime.ts b/src/common/hdl/hdlruntime.ts index 257dfec0..a57a6251 100644 --- a/src/common/hdl/hdlruntime.ts +++ b/src/common/hdl/hdlruntime.ts @@ -26,6 +26,7 @@ export class HDLModuleJS implements HDLModuleRunner { mod: HDLModuleDef; constpool: HDLModuleDef; + globals: {[name: string] : HDLVariableDef}; locals: {[name: string] : HDLVariableDef}; state: {[name: string] : HDLValue}; basefuncs: VerilatorUnit; @@ -43,13 +44,27 @@ export class HDLModuleJS implements HDLModuleRunner { this.constpool = constpool; this.basefuncs = {} as any; this.state = {}; //new Object(this.funcs) as any; + this.globals = {}; // set built-in functions Object.getOwnPropertyNames(Object.getPrototypeOf(this)).filter((f) => f.startsWith('$')).forEach((f) => { this.basefuncs[f] = this[f].bind(this); }) + // set initial state + if (this.constpool) { + var cp = new HDLModuleJS(this.constpool, null); + cp.init(); + Object.assign(this.state, cp.state); + Object.assign(this.globals, cp.globals); + } + for (var varname in this.mod.vardefs) { + var vardef = this.mod.vardefs[varname]; + this.globals[varname] = vardef; + this.state[varname] = this.defaultValue(vardef.dtype, vardef); + } // generate functions this.basefuncs = this.genFuncs({}); this.curfuncs = this.basefuncs; + /* for (var i=0; i<16; i++) { this.specfuncs[i] = this.genFuncs({ //reset:(i&1), @@ -58,16 +73,7 @@ export class HDLModuleJS implements HDLModuleRunner { test_CPU16_top$cpu$state:i }); } - // set initial state - if (this.constpool) { - var cp = new HDLModuleJS(this.constpool, null); - cp.init(); - Object.assign(this.state, cp.state); - } - for (var varname in this.mod.vardefs) { - var vardef = this.mod.vardefs[varname]; - this.state[varname] = this.defaultValue(vardef.dtype, vardef); - } + */ } init() { @@ -221,10 +227,12 @@ export class HDLModuleJS implements HDLModuleRunner { if (this.curconsts[e.refname] != null && !(options||{}).store) { this.constused++; return `${this.curconsts[e.refname]}`; - } else if (this.locals[e.refname]) + } else if (this.locals[e.refname]) { return `${e.refname}`; - else + } else if (this.globals[e.refname]) { return `o.${e.refname}`; + } else + throw new HDLError(e, `cannot find variable '${e.refname}'`) } else if (isVarDecl(e)) { this.locals[e.name] = e; let s = `var ${e.name}`; diff --git a/src/common/hdl/hdlwasm.ts b/src/common/hdl/hdlwasm.ts index ae75df3c..8f393b14 100644 --- a/src/common/hdl/hdlwasm.ts +++ b/src/common/hdl/hdlwasm.ts @@ -192,6 +192,7 @@ export class HDLModuleWASM implements HDLModuleRunner { this.maxMemoryMB = maxMemoryMB || 16; this.genMemory(); this.genFuncs(); + this.validate(); } async init() { @@ -311,23 +312,35 @@ export class HDLModuleWASM implements HDLModuleRunner { // generate global variables var state = new Struct(); this.globals = state; - // TODO: sort globals by size - // outputs are first - for (const [varname, vardef] of Object.entries(this.hdlmod.vardefs)) { + // sort globals by output flag and size + var vardefs = Object.values(this.hdlmod.vardefs); + function getVarDefSortKey(vdef: HDLVariableDef) { + var val = getDataTypeSize(vdef.dtype); // sort by size + if (!vdef.isOutput) val += 1000000; // outputs are first in list + return val; + } + vardefs.sort((a,b) => { + return getVarDefSortKey(a) - getVarDefSortKey(b); + }); + // outputs are contiguous so we can copy them to the trace buffer + // so we put them all first in the struct order + for (var vardef of vardefs) { if (vardef.isOutput) state.addVar(vardef); } if (state.len == 0) state.addEntry("___", 1); // ensure as least 8 output bytes for trace buffer state.alignTo(8); this.outputbytes = state.len; - // followed by inputs and internal vars - for (const [varname, vardef] of Object.entries(this.hdlmod.vardefs)) { + // followed by inputs and internal vars (arrays after logical types) + for (var vardef of vardefs) { if (!vardef.isOutput) state.addVar(vardef); } state.alignTo(8); this.statebytes = state.len; // followed by constant pool - for (const [varname, vardef] of Object.entries(this.constpool.vardefs)) { - state.addVar(vardef); + if (this.constpool) { + for (const vardef of Object.values(this.constpool.vardefs)) { + state.addVar(vardef); + } } state.alignTo(8); // and now the trace buffer @@ -339,53 +352,60 @@ export class HDLModuleWASM implements HDLModuleRunner { } private genFuncs() { - // function type (dsegptr) - var fsig = binaryen.createType([binaryen.i32]) - for (var block of this.hdlmod.blocks) { - // TODO: cfuncs only - var fnname = block.name; - // find locals of function - var fscope = new Struct(); - fscope.addEntry(GLOBAL, 4, binaryen.i32, null, true); // 1st param to function - // add __req local if change_request function - if (this.funcResult(block.name) == binaryen.i32) { - fscope.addEntry(CHANGEDET, 1, binaryen.i32, null, false); - } - this.pushScope(fscope); - block.exprs.forEach((e) => { - if (e && isVarDecl(e)) { - // TODO: make local reference types, instead of promoting local arrays to global - if (isReferenceType(e.dtype)) { - this.globals.addVar(e); - } else { - fscope.addVar(e); - } - } - }) - // create function body - var fbody = this.block2wasm(block, {funcblock:block}); - //var fbody = this.bmod.return(this.bmod.i32.const(0)); - var fret = this.funcResult(block.name); - var fref = this.bmod.addFunction(fnname, fsig, fret, fscope.getLocals(), fbody); - this.popScope(); - } - // export functions - for (var fname of VERILATOR_UNIT_FUNCTIONS) { - this.bmod.addFunctionExport(fname, fname); - } - // create helper functions - this.addHelperFunctions(); - // link imported functions - this.addImportedFunctions(); + // function type (dsegptr) + for (var block of this.hdlmod.blocks) { + this.genFunction(block); + } + // export functions + for (var fname of VERILATOR_UNIT_FUNCTIONS) { + this.bmod.addFunctionExport(fname, fname); + } + // create helper functions + this.addHelperFunctions(); + // link imported functions + this.addImportedFunctions(); + } + + private validate() { // validate wasm module //console.log(this.bmod.emitText()); //this.bmod.optimize(); if (!this.bmod.validate()) { console.log(this.bmod.emitText()); - throw new HDLError(null, `could not validate wasm module`); + throw new HDLError(null, `could not validate wasm module`); } } + private genFunction(block) { + // TODO: cfuncs only + var fnname = block.name; + // find locals of function + var fscope = new Struct(); + fscope.addEntry(GLOBAL, 4, binaryen.i32, null, true); // 1st param to function + // add __req local if change_request function + if (this.funcResult(block.name) == binaryen.i32) { + fscope.addEntry(CHANGEDET, 1, binaryen.i32, null, false); + } + this.pushScope(fscope); + block.exprs.forEach((e) => { + if (e && isVarDecl(e)) { + // TODO: make local reference types, instead of promoting local arrays to global + if (isReferenceType(e.dtype)) { + this.globals.addVar(e); + } else { + fscope.addVar(e); + } + } + }) + // create function body + var fbody = this.block2wasm(block, {funcblock:block}); + //var fbody = this.bmod.return(this.bmod.i32.const(0)); + var fret = this.funcResult(block.name); + var fsig = binaryen.createType([binaryen.i32]); // pass dataptr() + var fref = this.bmod.addFunction(fnname, fsig, fret, fscope.getLocals(), fbody); + this.popScope(); + } + private async genModule() { //console.log(this.bmod.emitText()); var wasmData = this.bmod.emitBinary(); @@ -946,6 +966,17 @@ export class HDLModuleWASM implements HDLModuleRunner { ]); } + _extend2wasm(e: HDLExtendop, opts:Options) { + var value = this.e2w(e.left); + var inst = this.i3264(e.dtype); + if (this.bmod.getFeatures() & binaryen.Features.SignExt) { + if (e.widthminv == 32 && e.width == 64) { + return this.bmod.i64.extend_u(value); + } + } + throw new HDLError(e, `cannot extend`); + } + _extends2wasm(e: HDLExtendop, opts:Options) { var value = this.e2w(e.left); var inst = this.i3264(e.dtype); diff --git a/src/common/hdl/vxmlparser.ts b/src/common/hdl/vxmlparser.ts index c622636f..7b99b8df 100644 --- a/src/common/hdl/vxmlparser.ts +++ b/src/common/hdl/vxmlparser.ts @@ -20,6 +20,7 @@ import { HDLAlwaysBlock, HDLArrayItem, HDLBinop, HDLBlock, HDLConstant, HDLDataT export class CompileError extends Error { constructor(obj: HDLSourceLocation|XMLNode, msg: string) { super(msg); + console.log(obj); Object.setPrototypeOf(this, CompileError.prototype); } } @@ -345,6 +346,9 @@ export class VerilogXMLParser implements HDLUnit { return block; } + visit_cuse(node: XMLNode) { // TODO? + } + visit_instance(node: XMLNode) : HDLInstanceDef { var instance : HDLInstanceDef = { $loc: this.parseSourceLocation(node), @@ -465,6 +469,11 @@ export class VerilogXMLParser implements HDLUnit { return dtype; } + visit_packarraydtype(node: XMLNode): HDLDataType { + // TODO: packed? + return this.visit_unpackarraydtype(node); + } + visit_unpackarraydtype(node: XMLNode): HDLDataType { let id = node.attrs['id']; let sub_dtype_id = node.attrs['sub_dtype_id']; @@ -530,7 +539,7 @@ export class VerilogXMLParser implements HDLUnit { return expr; } - visit_extends(node: XMLNode) : HDLUnop { + visit_extend(node: XMLNode) : HDLUnop { var unop = this.__visit_unop(node) as HDLExtendop; unop.width = parseInt(node.attrs['width']); unop.widthminv = parseInt(node.attrs['widthminv']); @@ -538,6 +547,10 @@ export class VerilogXMLParser implements HDLUnit { return unop; } + visit_extends(node: XMLNode) : HDLUnop { + return this.visit_extend(node); + } + __visit_binop(node: XMLNode) : HDLBinop { this.expectChildren(node, 2, 2); var expr: HDLBinop = { diff --git a/src/common/hdl/vxmltest.ts b/src/common/hdl/vxmltest.ts index 3f75ef43..0864d88a 100644 --- a/src/common/hdl/vxmltest.ts +++ b/src/common/hdl/vxmltest.ts @@ -107,6 +107,8 @@ async function testJSvsWASM() { } } +//testJS(); +testWASM(); //testJSvsWASM(); -testWASM().then(testJS).then(testJSvsWASM); +//testWASM().then(testJS).then(testJSvsWASM); diff --git a/src/platform/verilog.ts b/src/platform/verilog.ts index e18d7a0a..c200109f 100644 --- a/src/platform/verilog.ts +++ b/src/platform/verilog.ts @@ -474,7 +474,7 @@ var VerilogPlatform = function(mainElement, options) { } else { // not in sync, don't reset buffer (TODO: take some of the cycles back) //console.log('scanline', framey, scanlineCycles, nextlineCycles, n, hsyncStart, hsyncEnd); - nextlineCycles = maxLineCycles; + nextlineCycles = Math.min(maxLineCycles, n + scanlineCycles); } // exit when vsync starts and then stops if (tmod.trace.vsync) { @@ -550,6 +550,13 @@ var VerilogPlatform = function(mainElement, options) { } } + dispose() { + if (top) { + top.dispose(); + top = null; + } + } + // TODO: can this be async? async loadROM(title:string, output:any) { var unit = output as HDLUnit; @@ -558,11 +565,12 @@ var VerilogPlatform = function(mainElement, options) { { // initialize top module and constant pool var useWASM = true; - var _top = new (useWASM ? HDLModuleWASM : HDLModuleJS)(topmod, unit.modules['@CONST-POOL@']); + var topcons = useWASM ? HDLModuleWASM : HDLModuleJS; + var _top = new topcons(topmod, unit.modules['@CONST-POOL@']); _top.getFileData = (path) => current_project.filedata[path]; // external file provider await _top.init(); _top.powercycle(); - if (top) top.dispose(); + this.dispose(); top = _top; // create signal array var signals : WaveformSignal[] = []; diff --git a/test/cli/testverilog.js b/test/cli/testverilog.js index 5ba3fa27..7ae74258 100644 --- a/test/cli/testverilog.js +++ b/test/cli/testverilog.js @@ -1,5 +1,6 @@ var assert = require('assert'); +var _fs = require('fs'); var _path = require('path') var _cproc = require('child_process'); var fs = require('fs'); @@ -66,25 +67,44 @@ function testPerf(msg) { function compileVerilator(filename, code, callback, nerrors, depends) { global.postMessage = async function(msg) { + try { if (msg.errors && msg.errors.length) { console.log(msg.errors); assert.equal(nerrors||0, msg.errors.length, "errors"); } else { assert.equal(nerrors||0, 0, "errors"); - await loadPlatform(msg); + var platform = await loadPlatform(msg); //testPerf(msg); if (filename.indexOf('t_') >= 0) { - //assert.ok(verilog.vl_finished); + //assert.ok(platform.isBlocked() && !platform.isStopped()); } + platform.dispose(); } callback(null, msg); - }; - global.onmessage({ - data:{ - updates:[{path:_path.basename(filename), data:code}], - buildsteps:[{path:_path.basename(filename), platform:'verilog', tool:'verilator', files:depends}] + } catch (e) { + if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) { + process.exit(1); + } else { + //fs.unlinkSync(filename); + callback(e, null); } - }); + } + }; + try { + global.onmessage({ + data:{ + updates:[{path:_path.basename(filename), data:code}], + buildsteps:[{path:_path.basename(filename), platform:'verilog', tool:'verilator', files:depends}] + } + }); + } catch (e) { + if (e.msg && e.msg.indexOf('WebAssembly.Memory()') >= 0) { + process.exit(1); + } else { + //fs.unlinkSync(filename); + callback(e, null); + } + } } function testIcarus(filename) { @@ -97,13 +117,22 @@ function testVerilator(filename, disables, nerrors, depends) { //if (depends) testIcarus(filename); var csource = ab2str(fs.readFileSync(filename)); for (var i=0; i<(disables||[]).length; i++) - csource = "/* verilator lint_off " + disables[i] + " */ " + csource; + csource = "/* verilator lint_off " + disables[i] + " */\n" + csource; compileVerilator(filename, csource, done, nerrors||0, depends); }); } describe('Verilog Worker', function() { - + + var files = _fs.readdirSync('test/cli/verilog').filter(fn => fn.endsWith('.v')); + files = files.slice(0,80); + for (var fn of files) { + testVerilator('test/cli/verilog/' + fn, + ['UNDRIVEN','BLKSEQ','WIDTH','PINCONNECTEMPTY','SYNCASYNCNET','UNOPT','UNOPTFLAT','VARHIDDEN','EOFNEWLINE'] + ); + global.onmessage({data:{reset:true}}); + } + testVerilator('presets/verilog/hvsync_generator.v'); testVerilator('presets/verilog/digits10.v', null, null, ['digits10.v', 'hvsync_generator.v']); testVerilator('presets/verilog/scoreboard.v', null, null, ['scoreboard.v', 'digits10.v', 'hvsync_generator.v']); @@ -116,69 +145,5 @@ describe('Verilog Worker', function() { testVerilator('presets/verilog/sprite_scanline_renderer.v', null, null, ['sprite_scanline_renderer.v', 'ram.v', 'hvsync_generator.v']); testVerilator('presets/verilog/tile_renderer.v', null, null, ['tile_renderer.v', 'font_cp437_8x8.v', 'ram.v', 'hvsync_generator.v']); testVerilator('presets/verilog/cpu6502.v'); - // TODO: how to include files? have to pass buildsteps + files - //testVerilator('test/cli/verilog/t_tri_gate.v'); - testVerilator('test/cli/verilog/t_tri_gen.v', ['UNDRIVEN']); - testVerilator('test/cli/verilog/t_tri_graph.v', ['UNDRIVEN']); - testVerilator('test/cli/verilog/t_tri_ifbegin.v', ['UNDRIVEN']); - testVerilator('test/cli/verilog/t_tri_inout.v'); - testVerilator('test/cli/verilog/t_tri_inout2.v'); - testVerilator('test/cli/verilog/t_tri_pullup.v', ['UNDRIVEN']); - testVerilator('test/cli/verilog/t_tri_select_unsized.v', ['WIDTH']); - testVerilator('test/cli/verilog/t_tri_unconn.v', ['PINCONNECTEMPTY']); - testVerilator('test/cli/verilog/t_tri_various.v', ['UNDRIVEN']); - - testVerilator('test/cli/verilog/t_math_const.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_alw_combdly.v'); - testVerilator('test/cli/verilog/t_clk_first.v', ['UNDRIVEN','SYNCASYNCNET']); -/* TODO: fix tests - testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_clk_2in.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_order_comboclkloop.v'); -*/ - testVerilator('test/cli/verilog/t_gen_alw.v'); - testVerilator('test/cli/verilog/t_case_huge_sub3.v'); - - //testVerilator('test/cli/verilog/t_order.v'); - //testVerilator('test/cli/verilog/t_order_2d.v'); - //testVerilator('test/cli/verilog/t_order_a.v'); - //testVerilator('test/cli/verilog/t_order_b.v'); - //testVerilator('test/cli/verilog/t_order_clkinst.v'); - //testVerilator('test/cli/verilog/t_order_comboloop.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_order_first.v'); - //testVerilator('test/cli/verilog/t_order_loop_bad.v', ['BLKSEQ'], 10); - testVerilator('test/cli/verilog/t_order_multialways.v'); - testVerilator('test/cli/verilog/t_order_multidriven.v', ['UNDRIVEN']); - //testVerilator('test/cli/verilog/t_order_quad.v'); - testVerilator('test/cli/verilog/t_order_wireloop.v', ['UNOPT']); - - testVerilator('test/cli/verilog/t_mem.v'); - - testVerilator('test/cli/verilog/t_alw_dly.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_alw_split.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_alw_splitord.v', ['BLKSEQ']); - - testVerilator('test/cli/verilog/t_array_compare.v'); - - testVerilator('test/cli/verilog/t_math_arith.v', ['BLKSEQ']); - //testVerilator('test/cli/verilog/t_math_div.v'); - //testVerilator('test/cli/verilog/t_math_div0.v'); - - testVerilator('test/cli/verilog/t_clk_powerdn.v', ['BLKSEQ','SYNCASYNCNET']); - //testVerilator('test/cli/verilog/t_clk_latchgate.v', ['BLKSEQ']); - //testVerilator('test/cli/verilog/t_clk_latch.v'); - //testVerilator('test/cli/verilog/t_clk_gater.v', ['BLKSEQ']); - testVerilator('test/cli/verilog/t_clk_dsp.v'); - testVerilator('test/cli/verilog/t_clk_dpulse.v'); - testVerilator('test/cli/verilog/t_clk_condflop_nord.v'); - testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']); - - /* - it('should compile verilog example', function(done) { - var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v')); - compileVerilator(csource, done); - }); - */ }); diff --git a/test/cli/verilog/t_alw_nosplit.v b/test/cli/verilog/t_alw_nosplit.v new file mode 100644 index 00000000..53a29461 --- /dev/null +++ b/test/cli/verilog/t_alw_nosplit.v @@ -0,0 +1,132 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + // We expect none of these blocks to split. + // Blocks that can split should go in t_alw_split.v instead. + + reg [15:0] b_split_1, b_split_2; + always @ (/*AS*/m_din) begin + b_split_1 = m_din; + b_split_2 = b_split_1; + end + + reg [15:0] c_split_1, c_split_2; + always @ (/*AS*/m_din) begin + c_split_1 = m_din; + c_split_2 = c_split_1; + c_split_1 = ~m_din; + end + + always @ (posedge clk) begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + + reg [15:0] e_split_1, e_split_2; + always @ (posedge clk) begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + + reg [15:0] f_split_1, f_split_2; + always @ (posedge clk) begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + + reg [15:0] l_split_1, l_split_2; + always @ (posedge clk) begin + l_split_2 <= l_split_1; + l_split_1 <= l_split_2 | m_din; + end + + reg [15:0] z_split_1, z_split_2; + always @ (posedge clk) begin + z_split_1 <= 0; + z_split_1 <= ~m_din; + end + always @ (posedge clk) begin + z_split_2 <= 0; + z_split_2 <= z_split_1; + end + + reg [15:0] h_split_1; + reg [15:0] h_split_2; + reg [15:0] h_foo; + always @ (posedge clk) begin +// $write(" cyc = %x m_din = %x\n", cyc, m_din); + h_foo = m_din; + if (cyc > 2) begin + // This conditional depends on non-primary-input foo. + // Its dependency on foo should not be pruned. As a result, + // the dependencies of h_split_1 and h_split_2 on this + // conditional will also not be pruned, making them all + // weakly connected such that they'll end up in the same graph + // and we can't split. + if (h_foo == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + else begin + h_split_1 <= m_din; + h_split_2 <= ~m_din; + end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end // always @ (posedge clk) + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + end + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==4) begin + m_din <= 16'he11e; + if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; + if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; + if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; + if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; + if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; + if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; + if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test/cli/verilog/t_alw_reorder.v b/test/cli/verilog/t_alw_reorder.v new file mode 100644 index 00000000..2501945f --- /dev/null +++ b/test/cli/verilog/t_alw_reorder.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + reg [15:0] v1; + reg [15:0] v2; + reg [15:0] v3; + integer nosplit; + + always @ (posedge clk) begin + // write needed so that V3Dead doesn't kill v0..v3 + $write(" values %x %x %x\n", v1, v2, v3); + + // Locally-set 'nosplit' will prevent the if from splitting + // in splitAlwaysAll(). This whole always block should still be + // intact when we call splitReorderAll() which is the subject + // of this test. + nosplit = cyc; + if (nosplit > 2) begin + /* S1 */ v1 <= 16'h0; + /* S2 */ v1 <= m_din; + /* S3 */ if (m_din == 16'h0) begin + /* X1 */ v2 <= v1; + /* X2 */ v3 <= v2; + end + end + + // We expect to swap S2 and S3, and to swap X1 and X2. + // We can check that this worked by the absense of dly vars + // in the generated output; if the reorder fails (or is disabled) + // we should see dly vars for v1 and v2. + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc<=cyc+1; + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_alw_split_rst.v b/test/cli/verilog/t_alw_split_rst.v new file mode 100644 index 00000000..b0f411f5 --- /dev/null +++ b/test/cli/verilog/t_alw_split_rst.v @@ -0,0 +1,159 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] in = crc[3:0]; + wire clken = crc[4]; + wire rstn = !(cyc < 20 || (crc[11:8]==0)); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] ff_out; // From test of Test.v + wire [3:0] fg_out; // From test of Test.v + wire [3:0] fh_out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .ff_out (ff_out[3:0]), + .fg_out (fg_out[3:0]), + .fh_out (fh_out[3:0]), + // Inputs + .clk (clk), + .clken (clken), + .rstn (rstn), + .in (in[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h77979747fd1b3a5a + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test + (/*AUTOARG*/ + // Outputs + ff_out, fg_out, fh_out, + // Inputs + clk, clken, rstn, in + ); + + input clk; + input clken; + input rstn; + + input [3:0] in; + + output reg [3:0] ff_out; + reg [3:0] ff_10; + reg [3:0] ff_11; + reg [3:0] ff_12; + reg [3:0] ff_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + ff_10 <= 0; + ff_11 <= 0; + ff_12 <= 0; + ff_13 <= 0; + end + else begin + ff_10 <= in; + ff_11 <= ff_10; + ff_12 <= ff_11; + ff_13 <= ff_12; + ff_out <= ff_13; + end + end + + output reg [3:0] fg_out; + reg [3:0] fg_10; + reg [3:0] fg_11; + reg [3:0] fg_12; + reg [3:0] fg_13; + always @(posedge clk) begin + if (clken) begin + if ((rstn == 0)) begin + fg_10 <= 0; + fg_11 <= 0; + fg_12 <= 0; + fg_13 <= 0; + end + else begin + fg_10 <= in; + fg_11 <= fg_10; + fg_12 <= fg_11; + fg_13 <= fg_12; + fg_out <= fg_13; + end + end + end + + output reg [3:0] fh_out; + reg [3:0] fh_10; + reg [3:0] fh_11; + reg [3:0] fh_12; + reg [3:0] fh_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + fh_10 <= 0; + fh_11 <= 0; + fh_12 <= 0; + fh_13 <= 0; + end + else begin + if (clken) begin + fh_10 <= in; + fh_11 <= fh_10; + fh_12 <= fh_11; + fh_13[3:1] <= fh_12[3:1]; + fh_13[0] <= fh_12[0]; + fh_out <= fh_13; + end + end + end + + +endmodule diff --git a/test/cli/verilog/t_assert_basic.v b/test/cli/verilog/t_assert_basic.v new file mode 100644 index 00000000..0d718015 --- /dev/null +++ b/test/cli/verilog/t_assert_basic.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg toggle; + + integer cyc; initial cyc=1; + wire [7:0] cyc_copy = cyc[7:0]; + + always @ (negedge clk) begin + AssertionFalse1: assert (cyc<100); + assert (!(cyc==5) || toggle); + // FIX cover {cyc==3 || cyc==4}; + // FIX cover {cyc==9} report "DefaultClock,expect=1"; + // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; + end + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 + if (cyc==9) begin +`ifdef FAILING_ASSERTIONS + assert (0) else $info; + assert (0) else $info("Info message"); + assume (0) else $info("Info message from failing assumption"); + assert (0) else $info("Info message, cyc=%d", cyc); + InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); + InErrorBlock: assert (0) else $error("Error...."); + assert (0) else $fatal(1,"Fatal...."); +`endif + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_assert_casez.v b/test/cli/verilog/t_assert_casez.v new file mode 100644 index 00000000..359fc4ef --- /dev/null +++ b/test/cli/verilog/t_assert_casez.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + reg [1:0] value; + + initial begin + value = 2'b00; + unique casez (value) + 2'b00 : ; + 2'b01 : ; + 2'b1? : ; + endcase + value = 2'b11; + unique casez (value) + 2'b00 : ; + 2'b01 : ; + 2'b1? : ; + endcase + unique casez (1'b1) + default: ; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_assert_comp.v b/test/cli/verilog/t_assert_comp.v new file mode 100644 index 00000000..50fe0168 --- /dev/null +++ b/test/cli/verilog/t_assert_comp.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + if (0) begin + $info("User compile-time info"); + $warning("User compile-time warning"); + $error("User compile-time error"); + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_assert_cover.v b/test/cli/verilog/t_assert_cover.v new file mode 100644 index 00000000..b8028280 --- /dev/null +++ b/test/cli/verilog/t_assert_cover.v @@ -0,0 +1,158 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg toggle; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); + + Sub sub1 (.*); + Sub sub2 (.*); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input toggle, + input [31:0] cyc + ); + + // Simple cover + cover property (@(posedge clk) cyc==3); + + // With statement, in generate + generate if (1) begin + cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); + end + endgenerate + + // Labeled cover + cyc_eq_5: + cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + + // Using default clock + default clocking @(posedge clk); endclocking + cover property (cyc==6) $display("*COVER: Cyc==6"); + + // Disable statement + // Note () after disable are required + cover property (@(posedge clk) disable iff (toggle) cyc==8) + $display("*COVER: Cyc==8"); + cover property (@(posedge clk) disable iff (!toggle) cyc==8) + $stop; + + always_ff @ (posedge clk) begin + labeled_icov: cover (cyc==3 || cyc==4); + end + + // Immediate cover + labeled_imm0: cover #0 (cyc == 0); + labeled_immf: cover final (cyc == 0); + + // Immediate assert + labeled_imas: assert #0 (1); + assert final (1); + + //============================================================ + // Using a macro and generate + wire reset = (cyc < 2); + +`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) + + genvar i; + generate + for (i=0; i<32; i=i+1) + begin: cycval + CycCover_i: `covclk( cyc[i] ); + end + endgenerate + +`ifndef verilator // Unsupported + //============================================================ + // Using a more complicated property + property C1; + @(posedge clk) + disable iff (!toggle) + cyc==5; + endproperty + cover property (C1) $display("*COVER: Cyc==5"); + + // Using covergroup + // Note a covergroup is really inheritance of a special system "covergroup" class. + covergroup counter1 @ (posedge cyc); + // Automatic methods: stop(), start(), sample(), set_inst_name() + + // Each bin value must be <= 32 bits. Strange. + cyc_value : coverpoint cyc { + } + + cyc_bined : coverpoint cyc { + bins zero = {0}; + bins low = {1,5}; + // Note 5 is also in the bin above. Only the first bin matching is counted. + bins mid = {[5:$]}; + // illegal_bins // Has precidence over "first matching bin", creates assertion + // ignore_bins // Not counted, and not part of total + } + toggle : coverpoint (toggle) { + bins off = {0}; + bins on = {1}; + } + cyc5 : coverpoint (cyc==5) { + bins five = {1}; + } + + // option.at_least = {number}; // Default 1 - Hits to be considered covered + // option.auto_bin_max = {number}; // Default 64 + // option.comment = {string} + // option.goal = {number}; // Default 90% + // option.name = {string} + // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) + // option.weight = {number}; // Default 1 + + // CROSS + value_and_toggle: // else default is ___X__ + cross cyc_value, toggle; + endgroup + counter1 c1 = new(); +`endif + +endmodule + +module Sub + ( + input clk, + input integer cyc + ); + + // Simple cover, per-instance + pi_sub: + cover property (@(posedge clk) cyc == 3); +endmodule diff --git a/test/cli/verilog/t_assert_disable_iff.v b/test/cli/verilog/t_assert_disable_iff.v new file mode 100644 index 00000000..de74764d --- /dev/null +++ b/test/cli/verilog/t_assert_disable_iff.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Peter Monsson. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk)); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk + ); + +`ifdef FAIL_ASSERT_1 + assert property ( + @(posedge clk) disable iff (0) + 0 + ) else $display("wrong disable"); +`endif + + assert property ( + @(posedge clk) disable iff (1) + 0 + ); + + assert property ( + @(posedge clk) disable iff (1) + 1 + ); + + assert property ( + @(posedge clk) disable iff (0) + 1 + ); + + // + // Cover properties behave differently + // + + cover property ( + @(posedge clk) disable iff (1) + 1 + ) $stop; + + cover property ( + @(posedge clk) disable iff (1) + 0 + ) $stop; + + cover property ( + @(posedge clk) disable iff (0) + 1 + ) $display("*COVER: ok"); + + cover property ( + @(posedge clk) disable iff (0) + 0 + ) $stop; + +endmodule diff --git a/test/cli/verilog/t_assert_elab.v b/test/cli/verilog/t_assert_elab.v new file mode 100644 index 00000000..15b21a53 --- /dev/null +++ b/test/cli/verilog/t_assert_elab.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 + +module t; + localparam str = "string"; + function logic checkParameter(input logic [8:0] N); + $display("x is %d.", N); + if (N == 1) + return 0; + $fatal(1, "Parameter %d is invalid...%s and %s", N, str, "constant both work"); + endfunction + +`ifdef FAILING_ASSERTIONS + localparam x = checkParameter(5); +`else + localparam x = checkParameter(1); +`endif + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_assert_implication.v b/test/cli/verilog/t_assert_implication.v new file mode 100644 index 00000000..4a93b6d0 --- /dev/null +++ b/test/cli/verilog/t_assert_implication.v @@ -0,0 +1,130 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Peter Monsson. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk(clk), + .cyc(cyc)); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; +`ifdef TEST_VERBOSE + $display("cyc=%0d", cyc); +`endif + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input integer cyc + ); + +`ifdef FAIL_ASSERT_1 + assert property ( + @(posedge clk) + 1 |-> 0 + ) else $display("[%0t] wrong implication", $time); + + assert property ( + @(posedge clk) + 1 |=> 0 + ) else $display("[%0t] wrong implication", $time); + + assert property ( + @(posedge clk) + cyc%3==1 |=> cyc%3==1 + ) else $display("[%0t] wrong implication (step)", $time); + + assert property ( + @(posedge clk) + cyc%3==1 |=> cyc%3==0 + ) else $display("[%0t] wrong implication (step)", $time); + + assert property ( + @(posedge clk) disable iff (cyc == 3) + (cyc == 4) |=> 0 + ) else $display("[%0t] wrong implication (disable)", $time); + + assert property ( + @(posedge clk) disable iff (cyc == 6) + (cyc == 4) |=> 0 + ) else $display("[%0t] wrong implication (disable)", $time); + +`endif + + // Test |-> + assert property ( + @(posedge clk) + 1 |-> 1 + ); + + assert property ( + @(posedge clk) + 0 |-> 0 + ); + + assert property ( + @(posedge clk) + 0 |-> 1 + ); + + // Test |=> + assert property ( + @(posedge clk) + 1 |=> 1 + ); + + assert property ( + @(posedge clk) + 0 |=> 0 + ); + + assert property ( + @(posedge clk) + 0 |=> 1 + ); + + // Test correct handling of time step in |=> + assert property ( + @(posedge clk) + cyc%3==1 |=> cyc%3==2 + ); + + // Test correct handling of disable iff + assert property ( + @(posedge clk) disable iff (cyc < 3) + 1 |=> cyc > 3 + ); + + // Test correct handling of disable iff in current cycle + assert property ( + @(posedge clk) disable iff (cyc == 4) + (cyc == 4) |=> 0 + ); + + // Test correct handling of disable iff in previous cycle + assert property ( + @(posedge clk) disable iff (cyc == 5) + (cyc == 4) |=> 0 + ); + +endmodule diff --git a/test/cli/verilog/t_assert_on.v b/test/cli/verilog/t_assert_on.v new file mode 100644 index 00000000..55704fa6 --- /dev/null +++ b/test/cli/verilog/t_assert_on.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always @ (posedge clk) begin + assert (0); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_assert_property.v b/test/cli/verilog/t_assert_property.v new file mode 100644 index 00000000..f530048b --- /dev/null +++ b/test/cli/verilog/t_assert_property.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .cyc (cyc[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module Test + ( + input clk, + input [31:0] cyc + ); + +`ifdef FAIL_ASSERT_1 + assert property (@(posedge clk) cyc==3) + else $display("cyc != 3, cyc == %0d", cyc); + assume property (@(posedge clk) cyc==3) + else $display("cyc != 3, cyc == %0d", cyc); +`endif + +`ifdef FAIL_ASSERT_2 + assert property (@(posedge clk) cyc!=3); + assume property (@(posedge clk) cyc!=3); +`endif + + assert property (@(posedge clk) cyc < 100); + assume property (@(posedge clk) cyc < 100); + + restrict property (@(posedge clk) cyc==1); // Ignored in simulators + +// Unclocked is not supported: +// assert property (cyc != 6); + +endmodule diff --git a/test/cli/verilog/t_assert_question.v b/test/cli/verilog/t_assert_question.v new file mode 100644 index 00000000..8c6f4fe8 --- /dev/null +++ b/test/cli/verilog/t_assert_question.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + dout, + // Inputs + clk, sel, a, c + ); + + input clk; + input bit [3:0] sel; + input bit [3:0] a; + input bit c; + output bit dout; + + localparam logic DC = 1'b?; + + always_ff @(posedge clk) begin + unique casez(sel) + 4'b0000: dout <= a[0]; + 4'b001?: dout <= a[1]; + {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; + {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; + default: dout <= '0; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_assert_synth.v b/test/cli/verilog/t_assert_synth.v new file mode 100644 index 00000000..2a8f27e2 --- /dev/null +++ b/test/cli/verilog/t_assert_synth.v @@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg a; initial a = 1'b1; + reg b_fc; initial b_fc = 1'b0; + reg b_pc; initial b_pc = 1'b0; + reg b_oh; initial b_oh = 1'b0; + reg b_oc; initial b_oc = 1'b0; + wire a_l = ~a; + wire b_oc_l = ~b_oc; + + // Note we must ensure that full, parallel, etc, only fire during + // edges (not mid-cycle), and must provide a way to turn them off. + // SystemVerilog provides: $asserton and $assertoff. + + // verilator lint_off CASEINCOMPLETE + + always @* begin + // Note not all tools support directives on casez's +`ifdef ATTRIBUTES + case ({a,b_fc}) // synopsys full_case +`else + case ({a,b_fc}) +`endif + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + priority case ({a,b_fc}) + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + end + + always @* begin +`ifdef ATTRIBUTES + case (1'b1) // synopsys full_case parallel_case +`else + `ifdef FAILING_FULL + case (1'b1) // synopsys parallel_case + `else + case (1'b1) // synopsys parallel_full + `endif +`endif + a: ; + b_pc: ; + endcase + end + +`ifdef NOT_YET_VERILATOR // Unsupported + // ambit synthesis one_hot "a, b_oh" + // cadence one_cold "a_l, b_oc_l" +`endif + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==2) begin + a <= 1'b0; + b_fc <= 1'b1; + b_pc <= 1'b1; + b_oh <= 1'b1; + b_oc <= 1'b1; + end + if (cyc==3) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==4) begin +`ifdef FAILING_FULL + b_fc <= 1'b1; +`endif +`ifdef FAILING_PARALLEL + b_pc <= 1'b1; +`endif +`ifdef FAILING_OH + b_oh <= 1'b1; +`endif +`ifdef FAILING_OC + b_oc <= 1'b1; +`endif + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_assign_inline.v b/test/cli/verilog/t_assign_inline.v new file mode 100644 index 00000000..1b7033e8 --- /dev/null +++ b/test/cli/verilog/t_assign_inline.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Mike Thyer. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int cycle=0; + + // verilator lint_off UNOPTFLAT + reg [7:0] a_r; + wire [7:0] a_w; + reg [7:0] b_r; + reg [7:0] c_d_r, c_q_r; + + assign a_w = a_r; + + always @(*) begin + a_r = 0; + b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" + a_r = c_q_r; + c_d_r = c_q_r; + end + + // stimulus + checks + always @(posedge clk) begin + cycle <= cycle+1; + if (cycle==0) begin + c_q_r <= 8'b0; + end + else begin + c_q_r <= c_d_r+1; +`ifdef TEST_VERBOSE + $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same +`endif + end + if (cycle >= 10) begin + if (b_r==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_attr_parenstar.v b/test/cli/verilog/t_attr_parenstar.v new file mode 100644 index 00000000..d96199a7 --- /dev/null +++ b/test/cli/verilog/t_attr_parenstar.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + always @(*) begin + if (clk) begin end + end + + always @(* ) begin + if (clk) begin end + end + + // Not legal in some simulators, legal in others +// always @(* /*cmt*/ ) begin +// if (clk) begin end +// end + + // Not legal in some simulators, legal in others +// always @(* // cmt +// ) begin +// if (clk) begin end +// end + + always @ (* + ) begin + if (clk) begin end + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_bitsel_enum.v b/test/cli/verilog/t_bitsel_enum.v new file mode 100644 index 00000000..b23b7214 --- /dev/null +++ b/test/cli/verilog/t_bitsel_enum.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 + +module t_bitsel_enum + ( + output out0, + output out1 + ); + + localparam [6:0] CNST_VAL = 7'h22; + + enum logic [6:0] { + ENUM_VAL = 7'h33 + } MyEnum; + + assign out0 = CNST_VAL[0]; + // Not supported by NC-verilog nor VCS, but other simulators do + assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_bitsel_slice.v b/test/cli/verilog/t_bitsel_slice.v new file mode 100644 index 00000000..f943829c --- /dev/null +++ b/test/cli/verilog/t_bitsel_slice.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + logic [2:0] [1:0] in; + always @* in = crc[5:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [1:0] [1:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out/*[1:0][1:0]*/), + // Inputs + .clk (clk), + .in (in/*[2:0][1:0]*/)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out[1],out[0]}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hdc21e42d85441511 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + //bug717 + + input clk; + input logic [2:0][1:0] in; + + output logic [1:0][1:0] out; + + always @(posedge clk) begin + out <= in[2 -: 2]; + end +endmodule diff --git a/test/cli/verilog/t_blocking.v b/test/cli/verilog/t_blocking.v new file mode 100644 index 00000000..fa6ec64d --- /dev/null +++ b/test/cli/verilog/t_blocking.v @@ -0,0 +1,96 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer _mode; initial _mode=0; + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; + + reg [7:0] mode_d1r; + reg [7:0] mode_d2r; + reg [7:0] mode_d3r; + + // surefire lint_off ITENST + // surefire lint_off STMINI + // surefire lint_off NBAJAM + + always @ (posedge clk) begin // filp-flops with asynchronous reset + if (0) begin + _mode <= 0; + end + else begin + _mode <= _mode + 1; + if (_mode==0) begin + $write("[%0t] t_blocking: Running\n", $time); + a <= 8'd0; + b <= 8'd0; + c <= 8'd0; + end + else if (_mode==1) begin + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd1; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==2) begin + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd2; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==3) begin + if (a !== 8'd1) $stop; + if (b !== 8'd2) $stop; + if (c !== 8'd1) $stop; + end + else if (_mode==4) begin + if (mode_d3r != 8'd1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + always @ (posedge clk) begin + mode_d3r <= mode_d2r; + mode_d2r <= mode_d1r; + mode_d1r <= _mode[7:0]; + end + + reg [14:10] bits; + // surefire lint_off SEQASS + always @ (posedge clk) begin + if (_mode==1) begin + bits[14:13] <= 2'b11; + bits[12] <= 1'b1; + end + if (_mode==2) begin + bits[11:10] <= 2'b10; + bits[13] <= 0; + end + if (_mode==3) begin + if (bits !== 5'b10110) $stop; + end + end + +endmodule diff --git a/test/cli/verilog/t_case_deep.v b/test/cli/verilog/t_case_deep.v new file mode 100644 index 00000000..12335f6a --- /dev/null +++ b/test/cli/verilog/t_case_deep.v @@ -0,0 +1,343 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [33:0] in = crc[33:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] code; // From test of Test.v + wire [4:0] len; // From test of Test.v + wire next; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .next (next), + .code (code[31:0]), + .len (len[4:0]), + // Inputs + .clk (clk), + .in (in[33:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {26'h0, next, len, code}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'h5537fa30d49bf865 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + next, code, len, + // Inputs + clk, in + ); + + input clk; + input [33:0] in; + output next; + output [31:0] code; + output [4:0] len; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [31:0] code; + reg [4:0] len; + reg next; + // End of automatics + +/* +#!/usr/bin/env perl +use warnings; +srand(5); +my @used; +pat: + for (my $pat=0; 1; ) { + last if $pat > 196; + my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20; + my ($try, $val, $mask); + try: + for ($try=0; ; $try++) { + next pat if $try>50; + $val = 0; + for (my $bit=23; $bit>(23-$len); $bit--) { + my $b = int(rand()*2); + $val |= (1<<$bit) if $b; + } + $mask = (1<<(23-$len+1))-1; + for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { + next try if $used[$testval]; + } + last; + } + my $bits = ""; + my $val2 = 0; + for (my $bit=23; $bit>(23-$len); $bit--) { + my $b = ($val & (1<<$bit)); + $bits .= $b?'1':'0'; + } + for (my $testval = $val; $testval <= ($val + $mask); $testval++) { + $used[$testval]= 1; #printf "U%08x\n", $testval; + } + if ($try<90) { + printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" + ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); + $pat++; + } +} +*/ + + always @* begin + next = 1'b0; + code = 32'd0; + len = 5'b11111; + casez (in[31:8]) + 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; + 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; + 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; + 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; + 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; + 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; + 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; + 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; + 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; + 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; + 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; + 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; + 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; + 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; + 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; + 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; + 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; + 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; + 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; + 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; + 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; + 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; + 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; + 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; + 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; + 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; + 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; + 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; + 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; + 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; + 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; + 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; + 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; + 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; + 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; + 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; + 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; + 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; + 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; + 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; + 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; + 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; + 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; + 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; + 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; + 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; + 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; + 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; + 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; + 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; + 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; + 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; + 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; + 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; + 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; + 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; + 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; + 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; + 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; + 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; + 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; + 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; + 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; + 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; + 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; + 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; + 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; + 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; + 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; + 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; + 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; + 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; + 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; + 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; + 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; + 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; + 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; + 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; + 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; + 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; + 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; + 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; + 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; + 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; + 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; + 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; + 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; + 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; + 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; + 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; + 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; + 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; + 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; + 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; + 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; + 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; + 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; + 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; + 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; + 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; + 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; + 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; + 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; + 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; + 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; + 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; + 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; + 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; + 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; + 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; + 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; + 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; + 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; + 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; + 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; + 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; + 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; + 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; + 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; + 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; + 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; + 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; + 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; + 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; + 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; + 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; + 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; + 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; + 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; + 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; + 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; + 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; + 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; + 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; + 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; + 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; + 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; + 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; + 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; + 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; + 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; + 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; + 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; + 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; + 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; + 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; + 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; + 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; + 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; + 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; + 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; + 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; + 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; + 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; + 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; + 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; + 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; + 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; + 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; + 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; + 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; + 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; + 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; + 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; + 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; + 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; + 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; + 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; + 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; + 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; + 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; + 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; + 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; + 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; + 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; + 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; + 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; + 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; + 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; + 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; + 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; + 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; + 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; + 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; + 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; + 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; + 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; + 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; + 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; + 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; + 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; + 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; + 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; + 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; + 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; + 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; + 24'b000000??????????????????: begin + casez (in[33:32]) + 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; + 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; + 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; + default: ; + endcase + end + default: ; + endcase + end +endmodule diff --git a/test/cli/verilog/t_case_dupitems.v b/test/cli/verilog/t_case_dupitems.v new file mode 100644 index 00000000..8f38669e --- /dev/null +++ b/test/cli/verilog/t_case_dupitems.v @@ -0,0 +1,81 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [1:0] in = crc[1:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[1:0]), + // Inputs + .in (in[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {62'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'hbb2d9709592f64bd + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + input [1:0] in; + output reg [1:0] out; + always @* begin + // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? + case (in[1:0]) + 2'd0, 2'd1, 2'd2, 2'd3: begin + out = in; + end + endcase + end +endmodule diff --git a/test/cli/verilog/t_case_group.v b/test/cli/verilog/t_case_group.v new file mode 100644 index 00000000..0c7f1e62 --- /dev/null +++ b/test/cli/verilog/t_case_group.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 + +module t + ( + input i_clk, + input [6:0] i_input, + output logic o_output + ); + + always_ff @(posedge i_clk) + // verilator lint_off CASEINCOMPLETE + case (i_input) + 7'(92+2), + 7'(92+3): o_output <= 1'b1; + endcase + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_case_itemwidth.v b/test/cli/verilog/t_case_itemwidth.v new file mode 100644 index 00000000..67385ac9 --- /dev/null +++ b/test/cli/verilog/t_case_itemwidth.v @@ -0,0 +1,124 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Some inputs we'll set to random values + reg [6:0] addr; + reg [6:0] e0; + reg [5:0] e1; + reg [5:0] e2; + + wire [7:0] data; + reg [2:0] wrapcheck_a; + reg [2:0] wrapcheck_b; + + test test (/*AUTOINST*/ + // Outputs + .data (data[7:0]), + // Inputs + .addr (addr[6:0]), + .e0 (e0[6:0]), + .e1 (e1[5:0]), + .e2 (e2[5:0])); + + always @(/*AS*/addr) begin + case(addr[2:0]) + 3'd0+3'd0: wrapcheck_a = 3'h0; + 3'd0+3'd1: wrapcheck_a = 3'h1; + 3'd0+3'd2: wrapcheck_a = 3'h2; + 3'd0+3'd3: wrapcheck_a = 3'h3; + default: wrapcheck_a = 3'h4; + endcase + + case(addr[2:0]) + 3'd0+0: wrapcheck_b = 3'h0; + 3'd1+1: wrapcheck_b = 3'h1; + 3'd2+2: wrapcheck_b = 3'h2; + 3'd3+3: wrapcheck_b = 3'h3; + default: wrapcheck_b = 3'h4; + endcase + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + addr <= 7'h28; + e0 <= 7'h11; + e1 <= 6'h02; + e2 <= 6'h03; + end + if (cyc==2) begin + addr <= 7'h2b; + if (data != 8'h11) $stop; + end + if (cyc==3) begin + addr <= 7'h2c; + if (data != 8'h03) $stop; + if (wrapcheck_a != 3'h3) $stop; + if (wrapcheck_b != 3'h4) $stop; + end + if (cyc==4) begin + addr <= 7'h0; + if (data != 8'h00) $stop; + if (wrapcheck_a != 3'h4) $stop; + if (wrapcheck_b != 3'h2) $stop; + end + if (cyc==5) begin + if (data != 8'h00) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +/* verilator lint_off WIDTH */ +`define AI 7'h28 + +module test (/*AUTOARG*/ + // Outputs + data, + // Inputs + addr, e0, e1, e2 + ); + + output [7:0] data; + + input [6:0] addr; + input [6:0] e0; + input [5:0] e1, e2; + + reg [7:0] data; + + always @(/*AS*/addr or e0 or e1 or e2) + begin + case (addr) + `AI: data = {e0[6], 1'b0, e0[5:0]}; + `AI+1: data = e1; + `AI+2, + `AI+3: data = e2; + default: data = 0; + endcase + end + +endmodule + +// Local Variables: +// eval:(verilog-read-defines) +// verilog-auto-sense-defines-constant: t +// End: diff --git a/test/cli/verilog/t_case_onehot.v b/test/cli/verilog/t_case_onehot.v new file mode 100644 index 00000000..2f71d68e --- /dev/null +++ b/test/cli/verilog/t_case_onehot.v @@ -0,0 +1,96 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = (crc[1:0]==0 ? 3'd0 + : crc[1:0]==0 ? 3'd1 + : crc[1:0]==0 ? 3'd2 : 3'd4); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h704ca23e2a83e1c5 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input clk; + input [2:0] in; + output reg [31:0] out; + + localparam ST_0 = 0; + localparam ST_1 = 1; + localparam ST_2 = 2; + + always @(posedge clk) begin + case (1'b1) // synopsys parallel_case + in[ST_0]: out <= 32'h1234; + in[ST_1]: out <= 32'h4356; + in[ST_2]: out <= 32'h9874; + default: out <= 32'h1; + endcase + end +endmodule diff --git a/test/cli/verilog/t_case_orig.v b/test/cli/verilog/t_case_orig.v new file mode 100644 index 00000000..eb40b783 --- /dev/null +++ b/test/cli/verilog/t_case_orig.v @@ -0,0 +1,187 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg _ranit; + + reg rnd; + reg [2:0] a; + reg [2:0] b; + reg [31:0] wide; + + // surefire lint_off STMINI + initial _ranit = 0; + + wire sigone1 = 1'b1; + wire sigone2 = 1'b1; + reg ok; + + parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b?? + + // Large case statements should be well optimizable. + reg [2:0] anot; + always @ (/*AS*/a) begin + casez (a) + default: anot = 3'b001; + 3'd0: anot = 3'b111; + 3'd1: anot = 3'b110; + 3'd2: anot = 3'b101; + 3'd3: anot = 3'b101; + 3'd4: anot = 3'b011; + 3'd5: anot = 3'b010; + 3'd6: anot = 3'b001; // Same so folds with 7 + endcase + end + + always @ (posedge clk) begin + if (!_ranit) begin + _ranit <= 1; + rnd <= 1; + $write("[%0t] t_case: Running\n", $time); + // + a = 3'b101; + b = 3'b111; + // verilator lint_off CASEX + casex (a) + default: $stop; + 3'bx1x: $stop; + 3'b100: $stop; + 3'bx01: ; + endcase + casez (a) + default: $stop; + 3'b?1?: $stop; + 3'b100: $stop; + 3'b?01: ; + endcase + casez (a) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; + endcase + casez (b) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; +// {1'b0, 2'b??}: $stop; +// {1'b1, 2'b??}: ; + endcase + case(a[0]) + default: ; + endcase + casex(a) + default: ; + 3'b?0?: ; + endcase + // verilator lint_off CASEX + //This is illegal, the default occurs before the statements. + //case(a[0]) + // default: $stop; + // 1'b1: ; + //endcase + // + wide = 32'h12345678; + casez (wide) + default: $stop; + 32'h12345677, + 32'h12345678, + 32'h12345679: ; + endcase + // + ok = 0; + casez ({sigone1,sigone2}) + //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... + 2'b10, 2'b01: ; + 2'b00: ; + default: ok=1'b1; + endcase + if (ok !== 1'b1) $stop; + // + + if (rnd) begin + $write(""); + end + // + $write("*-* All Finished *-*\n"); + $finish; + end + end + + // Check parameters in case statements + parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. + parameter DSP_REGISTER_V = 6'h03; + + reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl + reg [5:0] reg_addr_2s; // Delayed version of reg_addr + reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases + reg [15:10] f_tmp_2s; // Delayed copy of F + reg p00_2s; + + initial begin + alu_ctl_2s = 3'h1; + reg_addr_2s = 6'h3; + ir_slave_2s= 0; + f_tmp_2s= 0; + casex ({alu_ctl_2s,reg_addr_2s, + ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], + f_tmp_2s[11:10]}) + default: p00_2s = 1'b0; + {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; + endcase + if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused + // + case ({1'b1, 1'b1}) + default: $stop; + {1'b1, p00_2s}: ; + endcase + end + + // Check wide overlapping cases + // surefire lint_off CSEOVR + parameter ANY_STATE = 7'h??; + reg [19:0] foo; + initial begin + foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; + casez (foo) + default: $stop; + {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; + {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; + endcase + end + initial begin + foo = 20'b1010; + casex (foo[3:0]) + default: $stop; + 4'b0xxx, + 4'b100x, + 4'b11xx: $stop; + 4'b1010: ; + endcase + end + initial begin + foo = 20'b1010; + ok = 1'b0; + // Test of RANGE(CONCAT reductions... + casex ({foo[3:2],foo[1:0],foo[3]}) + 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions + 5'bxx00x: $stop; + 5'bxx01x: $stop; + 5'bxx11x: $stop; + endcase + if (!ok) $stop; + end + +endmodule diff --git a/test/cli/verilog/t_case_reducer.v b/test/cli/verilog/t_case_reducer.v new file mode 100644 index 00000000..44e0a11b --- /dev/null +++ b/test/cli/verilog/t_case_reducer.v @@ -0,0 +1,279 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [7:0] operand_a = crc[7:0]; + wire [7:0] operand_b = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[6:0]), + // Inputs + .clk (clk), + .operand_a (operand_a[7:0]), + .operand_b (operand_b[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h8a78c2ec4946ac38 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + ( + // Inputs + input wire clk, + input wire [7:0] operand_a, // operand a + input wire [7:0] operand_b, // operand b + // Outputs + output wire [6:0] out + ); + + wire [6:0] clz_a; + wire [6:0] clz_b; + + clz u_clz_a + ( + // Inputs + .data_i (operand_a), + .out (clz_a)); + + clz u_clz_b + ( + // Inputs + .data_i (operand_b), + .out (clz_b)); + + assign out = clz_a - clz_b; +`ifdef TEST_VERBOSE + always @(posedge clk) + $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); +`endif + +endmodule + +`define def_0000_001x 8'b0000_0010, 8'b0000_0011 + +`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 + +`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011 +`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111 +`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx + +`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011 +`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111 +`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011 +`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111 + +`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011 +`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111 +`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011 +`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111 + +`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011 +`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111 +`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011 +`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111 + +`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011 +`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111 +`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011 +`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111 + +`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011 +`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111 +`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011 +`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111 + +`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011 +`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111 +`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011 +`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111 + +`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011 +`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111 +`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011 +`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111 + +`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011 +`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111 +`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011 +`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111 + +`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011 +`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111 +`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011 +`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111 + +`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011 +`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111 +`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011 +`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111 + +`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011 +`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111 +`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011 +`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111 + +`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011 +`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111 +`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011 +`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111 + +`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011 +`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111 +`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011 +`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111 + +`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011 +`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111 +`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011 +`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111 + +`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011 +`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111 +`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011 +`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111 + +`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx +`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx +`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx +`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx +`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx +`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx +`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx + +`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx +`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx +`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx +`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx +`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx +`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx +`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx +`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx + +`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \ + `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx +`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx +`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx + + + +module clz( + input wire [7:0] data_i, + output wire [6:0] out +); + + // ----------------------------- + // Reg declarations + // ----------------------------- + + reg [2:0] clz_byte0; + reg [2:0] clz_byte1; + reg [2:0] clz_byte2; + reg [2:0] clz_byte3; + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte0 = 3'b000; + `def_01xx_xxxx : clz_byte0 = 3'b001; + `def_001x_xxxx : clz_byte0 = 3'b010; + `def_0001_xxxx : clz_byte0 = 3'b011; + `def_0000_1xxx : clz_byte0 = 3'b100; + `def_0000_01xx : clz_byte0 = 3'b101; + `def_0000_001x : clz_byte0 = 3'b110; + 8'b0000_0001 : clz_byte0 = 3'b111; + 8'b0000_0000 : clz_byte0 = 3'b111; + default : clz_byte0 = 3'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte1 = 3'b000; + `def_01xx_xxxx : clz_byte1 = 3'b001; + `def_001x_xxxx : clz_byte1 = 3'b010; + `def_0001_xxxx : clz_byte1 = 3'b011; + `def_0000_1xxx : clz_byte1 = 3'b100; + `def_0000_01xx : clz_byte1 = 3'b101; + `def_0000_001x : clz_byte1 = 3'b110; + 8'b0000_0001 : clz_byte1 = 3'b111; + 8'b0000_0000 : clz_byte1 = 3'b111; + default : clz_byte1 = 3'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte2 = 3'b000; + `def_01xx_xxxx : clz_byte2 = 3'b001; + `def_001x_xxxx : clz_byte2 = 3'b010; + `def_0001_xxxx : clz_byte2 = 3'b011; + `def_0000_1xxx : clz_byte2 = 3'b100; + `def_0000_01xx : clz_byte2 = 3'b101; + `def_0000_001x : clz_byte2 = 3'b110; + 8'b0000_0001 : clz_byte2 = 3'b111; + 8'b0000_0000 : clz_byte2 = 3'b111; + default : clz_byte2 = 3'bxxx; + endcase + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte3 = 3'b000; + `def_01xx_xxxx : clz_byte3 = 3'b001; + `def_001x_xxxx : clz_byte3 = 3'b010; + `def_0001_xxxx : clz_byte3 = 3'b011; + `def_0000_1xxx : clz_byte3 = 3'b100; + `def_0000_01xx : clz_byte3 = 3'b101; + `def_0000_001x : clz_byte3 = 3'b110; + 8'b0000_0001 : clz_byte3 = 3'b111; + 8'b0000_0000 : clz_byte3 = 3'b111; + default : clz_byte3 = 3'bxxx; + endcase + + assign out = {4'b0000, clz_byte1}; + +endmodule // clz diff --git a/test/cli/verilog/t_case_x.v b/test/cli/verilog/t_case_x.v new file mode 100644 index 00000000..ac2ef544 --- /dev/null +++ b/test/cli/verilog/t_case_x.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + reg [3:0] value; + reg [3:0] valuex; + + // verilator lint_off CASEOVERLAP + // verilator lint_off CASEWITHX + // verilator lint_off CASEX + + // Note for Verilator Xs must become zeros, or the Xs may match. + + initial begin + value = 4'b1001; + valuex = 4'b1xxx; + case (value) + 4'b1xxx: $stop; + 4'b1???: $stop; + 4'b1001: ; + default: $stop; + endcase + case (valuex) + 4'b1???: $stop; + 4'b1xxx: ; + 4'b1001: ; + 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + // + casex (value) + 4'b100x: ; + default: $stop; + endcase + casex (value) + 4'b100?: ; + default: $stop; + endcase + casex (valuex) + 4'b100x: ; + default: $stop; + endcase + casex (valuex) + 4'b100?: ; + default: $stop; + endcase + // + casez (value) + 4'bxxxx: $stop; + 4'b100?: ; + default: $stop; + endcase + casez (valuex) + 4'b1xx?: ; + 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_cellarray.v b/test/cli/verilog/t_cellarray.v new file mode 100644 index 00000000..c7c6e32b --- /dev/null +++ b/test/cli/verilog/t_cellarray.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +// change these two parameters to see the speed differences +`define DATA_WIDTH 8 +`define REP_COUNT4 `DATA_WIDTH/4 +`define REP_COUNT2 `DATA_WIDTH/2 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + reg [3:0] count4 = 0; + reg [1:0] count2 = 0; + + reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; + reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; + reg [`DATA_WIDTH-1:0] res1; + reg [`DATA_WIDTH-1:0] res2; + reg [`DATA_WIDTH-1:0] res3; + reg [`DATA_WIDTH-1:0] res4; + + drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1)); + drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2)); + drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3)); + drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4)); + + always@(posedge clk) + begin + count2 <= count2 + 1; + count4 <= count4 + 1; + a <= {`REP_COUNT4{count4}}; + b <= {`REP_COUNT4{count4}}; + c <= {`REP_COUNT2{count2}}; + d <= {`REP_COUNT2{count2}}; + + if (res1 != (a)) begin + $stop; + end + if (res2 != (a&b)) begin + $stop; + end + if (res3 != (a&b&c)) begin + $stop; + end + if (res4 != (a&b&c&d)) begin + $stop; + end + + if (count4 > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + + +module drv1 + (input colSelA, + output datao + ); + assign datao = colSelA; +endmodule + +module drv2 + (input colSelA, + input colSelB, + output datao + ); + assign datao = colSelB & colSelA; +endmodule + +module drv3 + (input colSelA, + input colSelB, + input colSelC, + output datao + ); + assign datao = colSelB & colSelA & colSelC; + +endmodule + +module drv4 + (input colSelA, + input colSelB, + input colSelC, + input colSelD, + output datao + ); + assign datao = colSelB & colSelA & colSelC & colSelD; + +endmodule diff --git a/test/cli/verilog/t_chg_first.v b/test/cli/verilog/t_chg_first.v new file mode 100644 index 00000000..77015def --- /dev/null +++ b/test/cli/verilog/t_chg_first.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk, fastclk + ); + + input clk; + input fastclk; // surefire lint_off_line UDDIXN + + integer _mode; initial _mode=0; + + reg [31:0] ord1; initial ord1 = 32'h1111; + wire [31:0] ord2; + reg [31:0] ord3; + wire [31:0] ord4; + wire [31:0] ord5; + wire [31:0] ord6; + wire [31:0] ord7; + + // verilator lint_off UNOPT + t_chg_a a ( + .a(ord1), .a_p1(ord2), + .b(ord4), .b_p1(ord5), + .c(ord3), .c_p1(ord4), + .d(ord6), .d_p1(ord7) + ); + + // surefire lint_off ASWEMB + assign ord6 = ord5 + 1; + // verilator lint_on UNOPT + + always @ (/*AS*/ord2) ord3 = ord2 + 1; + + always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR + if (_mode==1) begin + //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); + //if (ord2 == 2 && ord7 != 7) $stop; + end + end + + always @ (posedge clk) begin + if (_mode==0) begin + $write("[%0t] t_chg: Running\n", $time); + _mode<=1; + ord1 <= 1; + end + else if (_mode==1) begin + _mode<=2; + if (ord7 !== 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module t_chg_a (/*AUTOARG*/ + // Outputs + a_p1, b_p1, c_p1, d_p1, + // Inputs + a, b, c, d + ); + input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; + input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; + input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; + input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; +endmodule diff --git a/test/cli/verilog/t_clk_gate_ext.v b/test/cli/verilog/t_clk_gate_ext.v new file mode 100644 index 00000000..02f59582 --- /dev/null +++ b/test/cli/verilog/t_clk_gate_ext.v @@ -0,0 +1,25 @@ +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg clk_en = 1'b0; + wire clk_gated = clk & clk_en; + wire [1:0] clks = {1'b0, clk_gated}; + + always @(posedge clks[0]) begin + $display("ERROR: clks[0] should not be active!"); + $stop; + end + + int cyc = 0; + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_clk_gater.v b/test/cli/verilog/t_clk_gater.v deleted file mode 100644 index b676228a..00000000 --- a/test/cli/verilog/t_clk_gater.v +++ /dev/null @@ -1,160 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - reg reset; - reg enable; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - // End of automatics - - // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; - - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .reset (reset), - .enable (enable), - .in (in[31:0])); - - wire [63:0] result = {32'h0, out}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - reset <= (cyc < 5); - enable <= cyc[4] || (cyc < 2); - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'h01e1553da1dcf3af - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, reset, enable, in - ); - - input clk; - input reset; - input enable; - input [31:0] in; - output [31:0] out; - - - // No gating - reg [31:0] d10; - always @(posedge clk) begin - d10 <= in; - end - - reg displayit; -`ifdef VERILATOR // Harder test - initial displayit = $c1("0"); // Something that won't optimize away -`else - initial displayit = '0; -`endif - - // Obvious gating + PLI - reg [31:0] d20; - always @(posedge clk) begin - if (enable) begin - d20 <= d10; // Obvious gating - if (displayit) begin - $display("hello!"); // Must glob with other PLI statements - end - end - end - - // Reset means second-level gating - reg [31:0] d30, d31a, d31b, d32; - always @(posedge clk) begin - d32 <= d31b; - if (reset) begin - d30 <= 32'h0; - d31a <= 32'h0; - d31b <= 32'h0; - d32 <= 32'h0; // Overlaps above, just to make things interesting - end - else begin - // Mix two outputs - d30 <= d20; - if (enable) begin - d31a <= d30; - d31b <= d31a; - end - end - end - - // Multiple ORs for gater - reg [31:0] d40a,d40b; - always @(posedge clk) begin - if (reset) begin - d40a <= 32'h0; - d40b <= 32'h0; - end - if (enable) begin - d40a <= d32; - d40b <= d40a; - end - end - - // Non-optimizable - reg [31:0] d91, d92; - reg [31:0] inverted; - always @(posedge clk) begin - inverted = ~d40b; - if (reset) begin - d91 <= 32'h0; - end - else begin - if (enable) begin - d91 <= inverted; - end - else begin - d92 <= inverted ^ 32'h12341234; // Inverted gating condition - end - end - end - - wire [31:0] out = d91 ^ d92; - -endmodule diff --git a/test/cli/verilog/t_clk_vecgen1.v b/test/cli/verilog/t_clk_vecgen1.v deleted file mode 100644 index fd4cd4ba..00000000 --- a/test/cli/verilog/t_clk_vecgen1.v +++ /dev/null @@ -1,124 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; - - wire [1:0] clkvec = crc[1:0]; - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] count; // From test of Test.v - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .count (count[1:0]), - // Inputs - .clkvec (clkvec[1:0])); - - // Aggregate outputs into a single result vector - wire [63:0] result = {62'h0, count}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; - sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; -`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - -`ifdef T_TEST1 -module Test - ( - input wire [1:0] clkvec, - // verilator lint_off MULTIDRIVEN - output reg [1:0] count - // verilator lint_on MULTIDRIVEN - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - initial count[igen] = 1'b0; - always @ (posedge clkvec[igen]) - count[igen] <= count[igen] + 1; - end - endgenerate - always @ (count) begin - $write("hi\n"); - end -endmodule -`endif - -`ifdef T_TEST2 -module Test - ( - input wire [1:0] clkvec, - // verilator lint_off MULTIDRIVEN - output reg [1:0] count - // verilator lint_on MULTIDRIVEN - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - // Unsupported: Count is multidriven, though if we did better analysis it wouldn't - // need to be. - initial count[igen] = 1'b0; - always @ (posedge clk_tmp) - count[igen] <= count[igen] + 1; - end - endgenerate -endmodule -`endif - -`ifdef T_TEST3 -module Test - ( - input wire [1:0] clkvec, - output wire [1:0] count - ); - genvar igen; - generate - for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - reg tmp_count = 1'b0; - always @ (posedge clk_tmp) begin - tmp_count <= tmp_count + 1; - end - assign count[igen] = tmp_count; - end - endgenerate -endmodule -`endif diff --git a/test/cli/verilog/t_clocker.v b/test/cli/verilog/t_clocker.v new file mode 100644 index 00000000..1694ae89 --- /dev/null +++ b/test/cli/verilog/t_clocker.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Simple test of CLkDATA +// +// Trigger the CLKDATA detection +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk, + res, + res8, + res16 + ); + input clk; + output reg res; + // When not inlining the below may trigger CLKDATA + output reg [7:0] res8; + output reg [15:0] res16; + + + wire [7:0] clkSet; + wire clk_1; + wire [2:0] clk_3; + wire [3:0] clk_4; + wire clk_final; + reg [7:0] count; + + + assign clkSet = {8{clk}}; + assign clk_4 = clkSet[7:4]; + assign clk_1 = clk_4[0];; + + // arraysel + assign clk_3 = {3{clk_1}}; + assign clk_final = clk_3[0]; + + // the following two assignment triggers the CLKDATA warning + // because on LHS there are a mix of signals both CLOCK and + // DATA + assign res8 = {clk_3, 1'b0, clk_4}; + assign res16 = {count, clk_3, clk_1, clk_4}; + + + initial + count = 0; + + + always @(posedge clk_final or negedge clk_final) begin + count = count + 1; + // the following assignment should trigger the CLKDATA warning + // because CLOCK signal is used as DATA in sequential block + res <= clk_final; + if ( count == 8'hf) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_concat_large.v b/test/cli/verilog/t_concat_large.v new file mode 100644 index 00000000..e01f9992 --- /dev/null +++ b/test/cli/verilog/t_concat_large.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + reg [32767:0] a; + + initial begin + // verilator lint_off WIDTHCONCAT + a = {32768{1'b1}}; + // verilator lint_on WIDTHCONCAT + if (a[32000] != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_concat_opt.v b/test/cli/verilog/t_concat_opt.v new file mode 100644 index 00000000..ae301428 --- /dev/null +++ b/test/cli/verilog/t_concat_opt.v @@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 +// +// The test was added together with the concat optimization. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] in_a; + reg [31:0] in_b; + reg [31:0] in_c; + reg [31:0] in_d; + reg [31:0] in_e; + reg [15:0] in_f; + wire [31:0] in_g; + + assign in_g = in_a << 4; + + reg [31:0] out_x; + reg [31:0] out_y; + reg [31:0] out_z; + reg [31:0] out_o; + reg [31:0] out_p; + reg [31:0] out_q; + + assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; + assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; + assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; + assign out_o = out_z | out_y; + assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; + assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + in_a <= cyc; + in_b <= cyc + 1; + in_c <= cyc + 3; + in_d <= cyc + 8; + in_e <= cyc; + in_f <= cyc[15:0]; + + if (out_x != (in_a & {2{in_f}})) + $stop; + if (out_y != (in_a&in_b)) + $stop; + if (out_z != (in_e&in_d&in_c)) + $stop; + if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) + $stop; + if (out_p != (in_a & {2{in_f}} | in_e)) + $stop; + if (out_q != (in_a ^ in_g)) + $stop; + + if (cyc==100) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_concat_sel.v b/test/cli/verilog/t_concat_sel.v new file mode 100644 index 00000000..33dc12a9 --- /dev/null +++ b/test/cli/verilog/t_concat_sel.v @@ -0,0 +1,74 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] a = crc[3:0]; + wire [3:0] b = crc[19:16]; + + // TEST + wire [3:0] out1 = {a,b}[2 +: 4]; + wire [3:0] out2 = {a,b}[5 -: 4]; + wire [3:0] out3 = {a,b}[5 : 2]; + wire [0:0] out4 = {a,b}[2]; + + // Aggregate outputs into a single result vector + wire [63:0] result = {51'h0, out4, out3, out2, out1}; + + initial begin + if ({16'h1234}[0] != 1'b0) $stop; + if ({16'h1234}[2] != 1'b1) $stop; + if ({16'h1234}[11:4] != 8'h23) $stop; + if ({16'h1234}[4+:8] != 8'h23) $stop; + if ({16'h1234}[11-:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[0] != 1'b0) $stop; + if ({8'h12, 8'h34}[2] != 1'b1) $stop; + if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; + if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test/cli/verilog/t_const.v b/test/cli/verilog/t_const.v new file mode 100644 index 00000000..43fa122f --- /dev/null +++ b/test/cli/verilog/t_const.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/); + + initial begin + // verilator lint_off WIDTH + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_crazy_sel.v b/test/cli/verilog/t_crazy_sel.v new file mode 100644 index 00000000..a3963752 --- /dev/null +++ b/test/cli/verilog/t_crazy_sel.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference +// as the select expression +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 + +interface foo_intf; + logic a; +endinterface + +function integer the_other_func (input integer val); + return val; +endfunction + +module t (/*AUTOARG*/); + genvar the_genvar; + generate + for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop + foo foo_inst(); + end + endgenerate + + bar bar_inst(); + + logic x; + assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; + //localparam N = 2; + //assign x = foo_loop[N].foo_inst.y; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module foo(); + logic y; +endmodule + +module bar(); + localparam THE_LP = 2; +endmodule diff --git a/test/cli/verilog/t_dynarray_param.v b/test/cli/verilog/t_dynarray_param.v new file mode 100644 index 00000000..72098b87 --- /dev/null +++ b/test/cli/verilog/t_dynarray_param.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Noam Gallmann. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/); + localparam int SIZES [3:0] = '{1,2,3,4}; + typedef int calc_sums_t [3:0]; + + localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); + function calc_sums_t calc_sums_array(int s[3:0], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_array[ii] = sum; + end + endfunction + +`ifndef VERILATOR + localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); +`endif + function calc_sums_t calc_sums_dyn(int s[], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_dyn[ii] = sum; + end + endfunction + + initial begin + `checkh(SIZES[0], 4); + `checkh(SIZES[1], 3); + `checkh(SIZES[2], 2); + `checkh(SIZES[3], 1); + + `checkh(SUMS_ARRAY[0], 4); + `checkh(SUMS_ARRAY[1], 7); + `checkh(SUMS_ARRAY[2], 9); + `checkh(SUMS_ARRAY[3], 10); + +`ifndef VERILATOR + `checkh(SUMS_DYN[0], 1); + `checkh(SUMS_DYN[1], 3); + `checkh(SUMS_DYN[2], 6); + `checkh(SUMS_DYN[3], 10); +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_fork_bbox.v b/test/cli/verilog/t_fork_bbox.v new file mode 100644 index 00000000..06f9ed03 --- /dev/null +++ b/test/cli/verilog/t_fork_bbox.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + initial begin + fork : fblk + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join : fblk + end + +endmodule diff --git a/test/cli/verilog/t_fork_label.v b/test/cli/verilog/t_fork_label.v new file mode 100644 index 00000000..a5d6112d --- /dev/null +++ b/test/cli/verilog/t_fork_label.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + initial begin + // Label checks + begin : b1 + end : b1 + // + b2 : begin + end : b2 + // With no statements this is a NOP + fork : f1 + join : f1 + // + f2: fork + join_any : f2 + // + fork + join_none + // With one statement this is supported and optimized to a begin/end + fork : fblk + begin + $write("*-* All Finished *-*\n"); + $finish; + end + join : fblk + end + +endmodule diff --git a/test/cli/verilog/t_func_endian.v b/test/cli/verilog/t_func_endian.v new file mode 100644 index 00000000..30d4ecc0 --- /dev/null +++ b/test/cli/verilog/t_func_endian.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire noswap = crc[32]; + wire nibble = crc[33]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .noswap (noswap), + .nibble (nibble), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h89522c3f5e5ca324) $stop; + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, noswap, nibble, in + ); + input clk; + + input noswap; + input nibble; + + input [31:0] in; + output [31:0] out; + + function [7:0] EndianSwap; + input Nibble; + input [7:0] Data; + begin + EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], + Data[4], Data[5], Data[6], Data[7] } + : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); + end + endfunction + + assign out[31:24] = (noswap ? in[31:24] + : EndianSwap(nibble, in[31:24])); + assign out[23:16] = (noswap ? in[23:16] + : EndianSwap(nibble, in[23:16])); + assign out[15:8] = (noswap ? in[15:8] + : EndianSwap(nibble, in[15:8])); + assign out[7:0] = (noswap ? in[7:0] + : EndianSwap(nibble, in[7:0])); +endmodule diff --git a/test/cli/verilog/t_func_first.v b/test/cli/verilog/t_func_first.v new file mode 100644 index 00000000..6aedc2fc --- /dev/null +++ b/test/cli/verilog/t_func_first.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + reg set_in_task; + + always @ (posedge clk) begin + if (cyc == 8'd0) begin + cyc <= 8'd1; + set_in_task <= 0; + end + if (cyc == 8'd1) begin + cyc <= 8'h2; + ttask; + end + if (cyc == 8'd2) begin + if (!set_in_task) $stop; + cyc <= 8'hf; + $write("*-* All Finished *-*\n"); + $finish; + end + end + + task ttask; + begin + set_in_task <= 1'b1; + end + endtask + +endmodule diff --git a/test/cli/verilog/t_func_flip.v b/test/cli/verilog/t_func_flip.v new file mode 100644 index 00000000..302b6b0d --- /dev/null +++ b/test/cli/verilog/t_func_flip.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define INT_RANGE 31:0 +`define INT_RANGE 31:0 // Duplicate identical defs are OK +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 511:0 + +module t (clk); + + // verilator lint_off WIDTH + + parameter WIDTH = 16; // Must be a power of 2 + parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) + parameter USE_BS = 1; // set to 1 for enable + + input clk; + + function [`VECTOR_RANGE] func_tree_left; + input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector + reg [`VECTOR_RANGE] flip; + begin + flip = 'd0; + func_tree_left = flip; + end + endfunction + + reg [WIDTH-1:0] a; // value to be shifted + reg [WIDTH-1:0] tree_left; + always @(a) begin : barrel_shift + tree_left = func_tree_left (a); + end // barrel_shift + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a = 5; + end + if (cyc==2) begin + $display ("%x\n",tree_left); + //if (tree_left != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + +endmodule diff --git a/test/cli/verilog/t_func_gen.v b/test/cli/verilog/t_func_gen.v new file mode 100644 index 00000000..410d7e0b --- /dev/null +++ b/test/cli/verilog/t_func_gen.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2012 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + genvar g; + logic [1:0] mask = 0; + generate + for (g=0; g<2; g++) + begin : picker + logic block_passed = 0; // Just for visualizing V3LinkDot debug + function [3:0] pick; + input [3:0] randnum; + pick = randnum+g[3:0]; + endfunction + always @(posedge clk) begin + if (pick(3)!=3+g[3:0]) $stop; + else mask[g] = 1'b1; + if (mask == 2'b11) begin // All iterations must be finished + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + endgenerate +endmodule diff --git a/test/cli/verilog/t_func_grey.v b/test/cli/verilog/t_func_grey.v new file mode 100644 index 00000000..2e77f477 --- /dev/null +++ b/test/cli/verilog/t_func_grey.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off _NETNM + // surefire lint_off STMINI + + input clk; + integer _mode; initial _mode = 0; + + wire [2:0] b3; reg [2:0] g3; + wire [5:0] b6; reg [5:0] g6; + + t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3)); + t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6)); + + always @ (posedge clk) begin + if (_mode==0) begin + _mode <= 1; + g3 <= 3'b101; + g6 <= 6'b110101; + end + else if (_mode==1) begin + if (b3 !== 3'b110) $stop; + if (b6 !== 6'b100110) $stop; + _mode <= 2; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +// Module gray2bin +// convert an arbitrary width gray coded number to binary. The conversion +// of a 4 bit gray (represented as "g") to binary ("b") would go as follows: +// b[3] = ^g[3] = g[3] +// b[2] = ^g[3:2] +// b[1] = ^g[3:1] +// b[0] = ^g[3:[SZ-1:0] cur0] + +module t_func_grey2bin (/*AUTOARG*/ + // Outputs + b, + // Inputs + g + ); + + // surefire lint_off STMFOR + + parameter SZ = 5; + output [SZ-1:0] b; + input [SZ-1:0] g; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [SZ-1:0] b; + // End of automatics + + integer i; + always @(/*AUTOSENSE*/g) + for (i=0; i> i); // surefire lint_off_line LATASS + +endmodule diff --git a/test/cli/verilog/t_func_lib.v b/test/cli/verilog/t_func_lib.v new file mode 100644 index 00000000..5882728b --- /dev/null +++ b/test/cli/verilog/t_func_lib.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_func_mlog2.v b/test/cli/verilog/t_func_mlog2.v new file mode 100644 index 00000000..4dfe03bf --- /dev/null +++ b/test/cli/verilog/t_func_mlog2.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + integer cyc; initial cyc=1; + integer sum; + integer cpre; + always @ (posedge clk) begin + if (cyc!=0) begin + cpre = cyc; + cyc <= cyc + 1; + if (cyc==1) begin + if (mlog2(32'd0) != 32'd0) $stop; + if (mlog2(32'd1) != 32'd0) $stop; + if (mlog2(32'd3) != 32'd2) $stop; + sum <= 32'd0; + end + else if (cyc<90) begin + // (cyc) so if we trash the variable things will get upset. + sum <= mlog2(cyc) + sum * 32'd42; + if (cpre != cyc) $stop; + end + else if (cyc==90) begin + if (sum !== 32'h0f12bb51) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + + function integer mlog2; + input [31:0] value; + integer i; + begin + if(value < 32'd1) begin + mlog2 = 0; + end + else begin + value = value - 32'd1; + mlog2 = 0; + for(i=0;i<32;i=i+1) begin + if(value > 32'd0) begin + mlog2 = mlog2 + 1; + end + value = value >> 1; + end + end + end + endfunction + +endmodule diff --git a/test/cli/verilog/t_func_numones.v b/test/cli/verilog/t_func_numones.v new file mode 100644 index 00000000..d1ff279e --- /dev/null +++ b/test/cli/verilog/t_func_numones.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + + reg [31:0] r32; + wire [3:0] w4; + wire [4:0] w5; + + assign w4 = NUMONES_8 ( r32[7:0] ); + assign w5 = NUMONES_16( r32[15:0] ); + + function [3:0] NUMONES_8; + input [7:0] i8; + reg [7:0] i8; + begin + NUMONES_8 = 4'b1; + end + endfunction // NUMONES_8 + + function [4:0] NUMONES_16; + input [15:0] i16; + reg [15:0] i16; + begin + NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] )); + end + endfunction + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + r32 <= 32'h12345678; + end + if (cyc==2) begin + if (w4 !== 1) $stop; + if (w5 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_func_outfirst.v b/test/cli/verilog/t_func_outfirst.v new file mode 100644 index 00000000..58943531 --- /dev/null +++ b/test/cli/verilog/t_func_outfirst.v @@ -0,0 +1,116 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define DDIFF_BITS 9 +`define AOA_BITS 8 +`define HALF_DDIFF `DDIFF_BITS'd256 +`define MAX_AOA `AOA_BITS'd255 +`define BURP_DIVIDER 9'd16 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; + wire reset = (cyc<7); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .AOA_B (AOA_B[`AOA_BITS-1:0]), + // Inputs + .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), + .reset (reset), + .clk (clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {56'h0, AOA_B}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h3a74e9d34771ad93 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + AOA_B, + // Inputs + DDIFF_B, reset, clk + ); + + input [`DDIFF_BITS-1:0] DDIFF_B; + input reset; + input clk; + output reg [`AOA_BITS-1:0] AOA_B; + + reg [`AOA_BITS-1:0] AOA_NEXT_B; + reg [`AOA_BITS-1:0] tmp; + + always @(posedge clk) begin + if (reset) begin + AOA_B <= 8'h80; + end + else begin + AOA_B <= AOA_NEXT_B; + end + end + + always @* begin + // verilator lint_off WIDTH + tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); + t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); + // verilator lint_on WIDTH + end + + task t_aoa_update; + output [`AOA_BITS-1:0] aoa_reg_next; + input [`AOA_BITS-1:0] aoa_reg; + input [`AOA_BITS-1:0] aoa_delta_update; + begin + if ((`MAX_AOA-aoa_reg)0; log2=log2+1) + arg = (arg >> 1); + end + endfunction + + always @ (posedge clk or negedge rst_n) + if (!rst_n) begin + pos1 <= 0; + pos2 <= 0; + end + else begin + pos1 <= pos1 + 1; + pos2 <= pos2 + 1; + end +endmodule diff --git a/test/cli/verilog/t_func_range.v b/test/cli/verilog/t_func_range.v new file mode 100644 index 00000000..c5a0cf3e --- /dev/null +++ b/test/cli/verilog/t_func_range.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + // verilator lint_off WIDTH + +`define INT_RANGE 31:0 +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 63:0 + + reg [`INT_RANGE] stashb, stasha, stashn, stashm; + + function [`VECTOR_RANGE] copy_range; + input [`VECTOR_RANGE] y; + input [`INT_RANGE] b; + input [`INT_RANGE] a; + + input [`VECTOR_RANGE] x; + input [`INT_RANGE] n; + input [`INT_RANGE] m; + + begin + copy_range = y; + stashb = b; + stasha = a; + stashn = n; + stashm = m; + end + endfunction + + parameter DATA_SIZE = 16; + parameter NUM_OF_REGS = 32; + + reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; + reg [DATA_SIZE-1:0] memread_rf_reg; + always @(memread_rf) begin : memread_convert + memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, + DATA_SIZE-'d1, DATA_SIZE-'d1); + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + memread_rf = 512'haa; + end + if (cyc==3) begin + if (stashb != 'd15) $stop; + if (stasha != 'd15) $stop; + if (stashn != 'd15) $stop; + if (stashm != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test/cli/verilog/t_func_real_param.v b/test/cli/verilog/t_func_real_param.v new file mode 100644 index 00000000..dad6ec3b --- /dev/null +++ b/test/cli/verilog/t_func_real_param.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug475 + +module t(); + + function real get_real_one; + input ignored; + get_real_one = 1.1; + endfunction + + localparam R_PARAM = get_real_one(1'b0); + localparam R_PARAM_2 = (R_PARAM > 0); + + generate + initial begin + if (R_PARAM != 1.1) $stop; + if (R_PARAM_2 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + endgenerate + +endmodule diff --git a/test/cli/verilog/t_func_regfirst.v b/test/cli/verilog/t_func_regfirst.v new file mode 100644 index 00000000..c45dfc61 --- /dev/null +++ b/test/cli/verilog/t_func_regfirst.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + reg [2:0] a; + reg [2:0] b; + reg q; + + f6 f6 (/*AUTOINST*/ + // Outputs + .q (q), + // Inputs + .a (a[2:0]), + .b (b[2:0]), + .clk (clk)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 3'b000; + b <= 3'b100; + end + if (cyc==2) begin + a <= 3'b011; + b <= 3'b001; + if (q != 1'b0) $stop; + end + if (cyc==3) begin + a <= 3'b011; + b <= 3'b011; + if (q != 1'b0) $stop; + end + if (cyc==9) begin + if (q != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module f6 (a, b, clk, q); + input [2:0] a; + input [2:0] b; + input clk; + output q; + reg out; + + function func6; + reg result; + input [5:0] src; + begin + if (src[5:0] == 6'b011011) begin + result = 1'b1; + end + else begin + result = 1'b0; + end + func6 = result; + end + endfunction + + wire [5:0] w6 = {a, b}; + always @(posedge clk) begin + out <= func6(w6); + end + + assign q = out; + +endmodule diff --git a/test/cli/verilog/t_func_under.v b/test/cli/verilog/t_func_under.v new file mode 100644 index 00000000..f4d8f015 --- /dev/null +++ b/test/cli/verilog/t_func_under.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [3:0] counter = 0; + integer l2; + function log2 (input [3:0] x); + integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; + endfunction + always @(posedge clk) begin + counter <= counter + 1; + l2 <= log2(counter); + // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): + $display("log2(%d) == %d", counter, log2(counter)); + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_func_under2.v b/test/cli/verilog/t_func_under2.v new file mode 100644 index 00000000..30d2515c --- /dev/null +++ b/test/cli/verilog/t_func_under2.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// bug598 + +module t (/*AUTOARG*/ + // Outputs + val, + // Inputs + clk + ); + + input clk; + output integer val; + integer dbg_addr = 0; + + function func1; + input en; + input [31:0] a; + func1 = en && (a == 1); + endfunction + + function func2; + input en; + input [31:0] a; + func2 = en && (a == 2); + endfunction + + always @(posedge clk) begin + case( 1'b1 ) + // This line is OK: + func1(1'b1, dbg_addr) : val = 1; + // This fails: + // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement + func2(1'b1, dbg_addr) : val = 2; + default : val = 0; + endcase + // + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test/cli/verilog/t_func_uninit.v b/test/cli/verilog/t_func_uninit.v new file mode 100644 index 00000000..c9eb8546 --- /dev/null +++ b/test/cli/verilog/t_func_uninit.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +function int zeroed; +endfunction + +function automatic integer what_bit; + input [31:0] a; + // what_bit = 0; + for (int i = 31; i >= 0; i = i - 1) begin + if (a[i] == 1'b1) begin + what_bit = i; + end + end +endfunction + +module t(/*AUTOARG*/); + + parameter ZERO = zeroed(); + + parameter PP = what_bit(0); + + initial begin + if (ZERO != 0) $stop; + if (PP != 'x) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test/cli/verilog/t_func_wide.v b/test/cli/verilog/t_func_wide.v new file mode 100644 index 00000000..ede40e84 --- /dev/null +++ b/test/cli/verilog/t_func_wide.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (clk); + input clk; + + reg [43:0] mi; + wire [31:0] mo; + muxtop um ( mi, mo); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + mi <= 44'h1234567890; + end + if (cyc==3) begin + if (mo !== 32'h12345678) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule + +module muxtop ( + input [ 43:0 ] i, + output reg [ 31:0 ] o + ); + + always @ ( i[43:0] ) // Verify we ignore ranges on always statement sense lists + o = MUX( i[39:0] ); + + function [31:0] MUX; + input [39:0] XX ; + begin + MUX = XX[39:8]; + end + endfunction +endmodule