verilog: added comments

presets/verilog/racing_game_cpu.v

@@ -146,6 +146,7 @@ module racing_game_cpu_top(clk, reset, hsync, vsync, hpaddle, vpaddle, rgb);
   wire r = display_on && (player_gfx || enemy_gfx || track_shoulder);
   wire g = display_on && (player_gfx || track_gfx);
   wire b = display_on && (enemy_gfx || track_shoulder);
+  // RGBI (in IBGR order, intensity is 4th bit)
   assign rgb = {1'b0,b,g,r};
   
   //////////// CPU program code

presets/verilog/test_hvsync.v

@@ -7,13 +7,15 @@ A simple test pattern using the hvsync_generator module.
 
 module test_hvsync_top(clk, reset, hsync, vsync, rgb);
 
-  input clk, reset;
-  output hsync, vsync;
-  output [2:0] rgb;
-  wire display_on;
-  wire [8:0] hpos;
-  wire [8:0] vpos;
+  input clk, reset;	// clock and reset signals (input)
+  output hsync, vsync;	// H/V sync signals (output)
+  output [2:0] rgb;	// RGB output (BGR order)
+  wire display_on;	// display_on signal
+  wire [8:0] hpos;	// 9-bit horizontal position
+  wire [8:0] vpos;	// 9-bit vertical position
 
+  // Include the H-V Sync Generator module and
+  // wire it to inputs, outputs, and wires.
   hvsync_generator hvsync_gen(
     .clk(clk),
     .reset(0),
@@ -24,9 +26,14 @@ module test_hvsync_top(clk, reset, hsync, vsync, rgb);
     .vpos(vpos)
   );
 
+  // Assign each color bit to individual wires.
   wire r = display_on && (((hpos&7)==0) || ((vpos&7)==0));
   wire g = display_on && vpos[4];
   wire b = display_on && hpos[4];
+  
+  // Concatenation operator merges the red, green, and blue signals
+  // into a single 3-bit vector, which is assigned to the 'rgb'
+  // output. The IDE expects this value in BGR order.
   assign rgb = {b,g,r};
 
 endmodule