fixed hsync generator to use assign

presets/verilog/ball_paddle.v

@@ -83,10 +83,8 @@ module ball_paddle_top(clk, reset, hpaddle, hsync, vsync, rgb);
   reg [6:0] brick_index;
   wire brick_gfx = lr_border || (brick_present && vpos[2:0] != 0 && hpos[3:1] != 4);
   
-  wire visible_clk = clk & display_on;
-
   // scan bricks: compute brick_index and brick_present flag
-  always @(posedge visible_clk)
+  always @(posedge clk)
     // see if we are scanning brick area
     if (vpos[8:6] == 1 && !lr_border)
     begin
@@ -121,7 +119,7 @@ module ball_paddle_top(clk, reset, hpaddle, hsync, vsync, rgb);
   /* verilator lint_on MULTIDRIVEN */
 
   // compute ball collisions with paddle and playfield
-  always @(posedge visible_clk)
+  always @(posedge clk)
     if (ball_pixel_collide) begin
       // did we collide w/ paddle?
       if (paddle_gfx) begin
@@ -135,7 +133,7 @@ module ball_paddle_top(clk, reset, hpaddle, hsync, vsync, rgb);
     end
 
   // compute ball collisions with brick and increment score
-  always @(posedge visible_clk)
+  always @(posedge clk)
     if (ball_pixel_collide && brick_present) begin
       brick_array[brick_index] <= 0;
       incscore <= 1; // increment score

presets/verilog/hvsync_generator.v

@@ -31,32 +31,28 @@ module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
   wire hmaxxed = (hpos == H_MAX) || reset;
   wire vmaxxed = (vpos == V_MAX) || reset;
   
-  // increment horizontal position counter
+  // horizontal position counter
   always @(posedge clk)
   begin
+    hsync <= (hpos>=H_SYNC_START && hpos<=H_SYNC_END);
     if(hmaxxed)
       hpos <= 0;
     else
       hpos <= hpos + 1;
   end
 
-  // increment vertical position counter
+  // vertical position counter
   always @(posedge clk)
   begin
+    vsync <= (vpos>=V_SYNC_START && vpos<=V_SYNC_END);
     if(hmaxxed)
-      if (!vmaxxed)
-        vpos <= vpos + 1;
-      else
+      if (vmaxxed)
         vpos <= 0;
+      else
+        vpos <= vpos + 1;
   end
   
-  // compute hsync + vsync + display_on signals
-  always @(posedge clk)
-  begin
-    hsync <= (hpos>=H_SYNC_START && hpos<=H_SYNC_END);
-    vsync <= (vpos>=V_SYNC_START && vpos<=V_SYNC_END);
-    display_on <= (hpos<H_DISPLAY) && (vpos<V_DISPLAY);
-  end
+  assign display_on = (hpos<H_DISPLAY) && (vpos<V_DISPLAY);
 
 endmodule
 

src/worker/workermain.js

@@ -1071,11 +1071,13 @@ function compileVerilator(code, platform, options) {
   writeDependencies(options.dependencies, FS, errors);
   starttime();
   verilator_mod.callMain(["--cc", "-O3",
-    "-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED",
+    "-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat',
     "--x-assign", "fast", "--noassert", "--pins-bv", "33",
     "--top-module", topmod, topmod+".v"]);
   endtime("compile");
-  if (errors.length) return {errors:errors};
+  if (errors.length) {
+    return {errors:errors};
+  }
   try {
     var h_file = FS.readFile("obj_dir/V"+topmod+".h", {encoding:'utf8'});
     var cpp_file = FS.readFile("obj_dir/V"+topmod+".cpp", {encoding:'utf8'});