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tests: createTestDOM() function

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This commit is contained in:
Steven Hugg 2020-07-27 08:04:48 -05:00
parent a5c69fa274
commit 68f19fbf11
5 changed files with 22 additions and 13 deletions
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4
doc/notes.txt
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@ -110,6 +110,7 @@ TODO:
- can't add control instructions b/c of split - can't add control instructions b/c of split
- bad error msg if >2 moduels and top module doesn't match filename - bad error msg if >2 moduels and top module doesn't match filename
- separate Scope View - separate Scope View
- Audio doesn't work if clock != default
- single-stepping vector games makes screen fade - single-stepping vector games makes screen fade
- break on stack overflow, illegal op, bad access, BRK, etc - break on stack overflow, illegal op, bad access, BRK, etc
- show in scope instead? - show in scope instead?
@ -157,6 +158,7 @@ TODO:
- importing from subtree commits to root anyway - importing from subtree commits to root anyway
- publishing Markdown file loads default file? - publishing Markdown file loads default file?
- better text/binary detection (e.g. 0xa9 copyright) - better text/binary detection (e.g. 0xa9 copyright)
- going into repo chooses wrong file if republished with different main
- keyboard shortcuts - keyboard shortcuts
- ctrl+alt+l on ubuntu locks screen - ctrl+alt+l on ubuntu locks screen
- alt-D doesn't work anymore - alt-D doesn't work anymore
@ -196,6 +198,8 @@ TODO:
- more stuff like 7800 display lists - more stuff like 7800 display lists
- don't include start/end line on platforms w/o raster timing - don't include start/end line on platforms w/o raster timing
- memory map shows subroutine symbol even after RTS - memory map shows subroutine symbol even after RTS
- BIOS symbols
WEB WORKER FORMAT WEB WORKER FORMAT

2
src/worker/workermain.ts
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@ -1653,7 +1653,7 @@ function compileVerilator(step:BuildStep) {
}); });
starttime(); starttime();
try { try {
var args = ["--cc", "-O3", "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod, var args = ["--cc", "-O3"/*abcdefstzsuka*/, "-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod,
"-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat', "-Wall", "-Wno-DECLFILENAME", "-Wno-UNUSED", '--report-unoptflat',
"--x-assign", "fast", "--noassert", "--pins-bv", "33", "--x-assign", "fast", "--noassert", "--pins-bv", "33",
"--top-module", topmod, step.path] "--top-module", topmod, step.path]

11
test/cli/testplatforms.js
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@ -4,16 +4,7 @@ var fs = require('fs');
var wtu = require('./workertestutils.js'); var wtu = require('./workertestutils.js');
var PNG = require('pngjs').PNG; var PNG = require('pngjs').PNG;
const jsdom = require('jsdom'); const dom = createTestDOM();
const { JSDOM } = jsdom;
//const { window } = new JSDOM();
const dom = new JSDOM(`<!DOCTYPE html><div id="emulator"><div id="javatari-screen"></div></div>`);
global.window = dom.window;
global.document = dom.window.document;
dom.window.Audio = null;
global.Image = function() { }
global['$'] = require("jquery/jquery.min.js");
includeInThisContext('src/common/cpu/6809.js'); includeInThisContext('src/common/cpu/6809.js');
includeInThisContext("javatari.js/release/javatari/javatari.js"); includeInThisContext("javatari.js/release/javatari/javatari.js");
Javatari.AUTO_START = false; Javatari.AUTO_START = false;

6
test/cli/testverilog.js
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@ -2,6 +2,7 @@
var assert = require('assert'); var assert = require('assert');
var fs = require('fs'); var fs = require('fs');
var wtu = require('./workertestutils.js'); var wtu = require('./workertestutils.js');
createTestDOM();
var emu = require('gen/common/emu.js'); var emu = require('gen/common/emu.js');
var verilog = require('gen/platform/verilog.js'); var verilog = require('gen/platform/verilog.js');
@ -21,7 +22,7 @@ function loadPlatform(msg) {
platform.loadROM("ROM", msg.output); platform.loadROM("ROM", msg.output);
platform.loadROM("ROM", msg.output); platform.loadROM("ROM", msg.output);
verilog.vl_finished = verilog.vl_stopped = false; verilog.vl_finished = verilog.vl_stopped = false;
for (var i=0; i<10000 && !(verilog.vl_finished||verilog.vl_stopped); i++) { for (var i=0; i<100000 && !(verilog.vl_finished||verilog.vl_stopped); i++) {
platform.tick(); platform.tick();
} }
assert.ok(!verilog.vl_stopped); assert.ok(!verilog.vl_stopped);
@ -42,7 +43,7 @@ function loadPlatform(msg) {
function testPerf(msg) { function testPerf(msg) {
var platform = new VerilogPlatform(); var platform = new VerilogPlatform();
platform.loadROM("ROM", msg.output); platform.loadROM("ROM", msg.output);
var niters = 2000000; var niters = 5000000;
console.time("before"); console.time("before");
for (var i=0; i<niters; i++) for (var i=0; i<niters; i++)
@ -154,6 +155,7 @@ describe('Verilog Worker', function() {
testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']); testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']);
testVerilator('presets/verilog/hvsync_generator.v'); testVerilator('presets/verilog/hvsync_generator.v');
testVerilator('presets/verilog/cpu6502.v');
/* /*
it('should compile verilog example', function(done) { it('should compile verilog example', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v')); var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v'));

12
test/cli/workertestutils.js
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@ -127,3 +127,15 @@ global.fetch = function(path) {
} }
}); });
} }
global.createTestDOM = function() {
const jsdom = require('jsdom');
const { JSDOM } = jsdom;
const dom = new JSDOM(`<!DOCTYPE html><div id="emulator"><div id="javatari-screen"></div></div>`);
global.window = dom.window;
global.document = dom.window.document;
global['$'] = require("jquery/jquery.min.js");
dom.window.Audio = null;
global.Image = function() { }
return dom;
}