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https://github.com/sehugg/8bitworkshop.git
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add binaryen.js to lib/
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parent
b9a0de6cac
commit
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1
Makefile
1
Makefile
@ -15,6 +15,7 @@ all:
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cp node_modules/localforage/dist/localforage.min.js ./lib/
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cp node_modules/jszip/dist/jszip.min.js ./lib/
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cp node_modules/file-saver/dist/*.min.js ./lib/
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cp node_modules/binaryen/index.js ./lib/binaryen.js
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cp unicorn.js/dist/unicorn-arm.min.js ./unicorn.js/demos/externals/capstone-arm.min.js ./lib/
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cp gif.js/dist/* ./lib/
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cd jsnes && npm i
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351
lib/binaryen.js
Normal file
351
lib/binaryen.js
Normal file
File diff suppressed because one or more lines are too long
@ -1026,10 +1026,18 @@ export class HDLModuleWASM implements HDLModuleRunner {
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if (hasDataType(e.left) && hasDataType(e.right)) {
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var lsize = getDataTypeSize(e.left.dtype);
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var rsize = getDataTypeSize(e.right.dtype);
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if (lsize < rsize && upcastLeft)
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var ltype = getBinaryenType(lsize);
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var rtype = getBinaryenType(rsize);
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if (ltype != rtype && rsize > lsize && upcastLeft) {
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//console.log(e, lsize, rsize);
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left = this.castexpr(left, e.left.dtype, e.right.dtype);
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else if (rsize < lsize && upcastRight)
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e.left.dtype = e.right.dtype;
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} else if (ltype != rtype && lsize > rsize && upcastRight) {
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//console.log(e, lsize, rsize);
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right = this.castexpr(right, e.right.dtype, e.left.dtype);
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e.right.dtype = e.left.dtype;
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} else if (ltype != rtype)
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{} // TODO: throw new HDLError(e, `wrong argument sizes`);
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}
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var rtn = f_op(left, right);
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return rtn;
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@ -507,6 +507,14 @@ export class VerilogXMLParser implements HDLUnit {
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throw new CompileError(null, `structs not supported`);
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}
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visit_constdtype(node: XMLNode) {
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// TODO? throw new CompileError(null, `constant data types not supported`);
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}
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visit_paramtypedtype(node: XMLNode) {
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// TODO? throw new CompileError(null, `constant data types not supported`);
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}
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visit_unpackarraydtype(node: XMLNode): HDLDataType {
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let id = node.attrs['id'];
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let sub_dtype_id = node.attrs['sub_dtype_id'];
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@ -190,7 +190,7 @@ var VerilogPlatform = function(mainElement, options) {
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await loadScript('./gen/common/hdl/hdltypes.js');
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await loadScript('./gen/common/hdl/hdlruntime.js');
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await loadScript('./gen/common/hdl/hdlwasm.js');
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await loadScript('./node_modules/binaryen/index.js'); // TODO: path?
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await loadScript('./lib/binaryen.js'); // TODO: path?
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video = new RasterVideo(mainElement,videoWidth,videoHeight,{overscan:true});
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video.create();
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poller = setKeyboardFromMap(video, switches, VERILOG_KEYCODE_MAP, (o,key,code,flags) => {
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228
test/cli/verilog/darksocv.v
Normal file
228
test/cli/verilog/darksocv.v
Normal file
@ -0,0 +1,228 @@
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`define __BAUD__ '0
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module darksocv_top
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(
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input b,
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c,
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output d,
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[3:0] LED,
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DEBUG
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);
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wire e = b;
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`ifdef g
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`else
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wire CLK = e;
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wire h [];
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reg [31:0] i [7];
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`endif
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wire [31:0] IADDR;
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wire [31:0] aa;
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wire [31:0] j;
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wire [31:0] DATAO;
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wire [31:0] k;
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wire l,m;
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wire [3:0] ab;
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wire n [];
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reg [5:0] o = 0;
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`ifdef p
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`else
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reg [31:0] q
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`ifdef r
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`else
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;
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assign j = q;
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`endif
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always@(posedge CLK)
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begin
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`ifdef d
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`else
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q <= i;
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`endif
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end
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reg [31:0] s;
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`ifdef r
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`endif
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always@(posedge CLK)
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begin
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`ifdef d
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`else
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s <= i;
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`ifdef d
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`else
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i[aa][ 7: 0 ] <= DATAO[ 7: 0 ];
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`endif
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`endif
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end
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assign k = s;
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`endif
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wire [7:0] u;
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ae
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v
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(
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CLK,
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h,
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m,
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l,
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ab,
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k,
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n,
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u[1],
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c,
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d,
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DEBUG
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);
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af
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w
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(
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`ifdef ag
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`else
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CLK,
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`endif
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h,
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c,
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j,
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IADDR,
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.aa,
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`ifdef x
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`else
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.k,
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.DATAO,
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ab,
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l,
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m,
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`endif
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y,
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DEBUG
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);
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wire y ;
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assign LED = o[3:0];
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endmodule
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`define UART_STATE_IDLE 6
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`define UART_STATE_START 7
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module ae
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(
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input CLK,
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h,
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m,
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l,
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[ 3:0] z,
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[31:0] k,
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output [31:0] DATAO,
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output IRQ,
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input RXD,
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output TXD,
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[3:0] DEBUG
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);
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reg [15:0] UART_TIMER = `__BAUD__;
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`ifdef ah
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`else
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reg UART_XACK = 0;
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`endif
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reg [ 3:0] UART_XSTATE= 0;
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`ifdef ah
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`else
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reg [ 7:0] UART_RFIFO = 0;
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reg UART_RACK = 0;
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`endif
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reg [ 3:0] UART_RSTATE= 0;
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`ifdef ah
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`else
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wire [7:0] UART_STATE = { 6'd0, UART_RACK, UART_XACK };
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`endif
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assign IRQ = 0;
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`ifdef a
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`else
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assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
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assign TXD = UART_XSTATE==`UART_STATE_START ;
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`endif
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assign DEBUG = { RXD, TXD, UART_XSTATE!=`UART_STATE_IDLE, UART_RSTATE!=`UART_STATE_IDLE };
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endmodule
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`define LCC 'b00000_11
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module af
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(
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input CLK,
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h,
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c,
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[31:0] j,
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output [31:0] IADDR,
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input [31:0] k,
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output [31:0] DATAO,
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aa,
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`ifdef x
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`else
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[ 3:0] ab,
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output l,
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m,
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`endif
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y,
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[3:0] DEBUG
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);
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wire [31:0] aj = 0;
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reg [31:0] al;
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reg XLCC, am , an=1;
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reg [31:0] ao;
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reg [31:0] ap;
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always@(posedge CLK)
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begin
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al <= an ? al : j;
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XLCC <= an ? XLCC : j==`LCC;
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am <= aq
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;
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ao <=
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aj;
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ap <= aj;
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end
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`ifdef ag
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`else
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reg ar ;
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`ifdef as
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`else
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reg [4:0] DPTR = al[19:15];
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wire [4:0] at = al[24:20];
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`endif
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`endif
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wire [31:0] au =
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ap;
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wire LCC = XLCC;
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wire aq = am;
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`ifdef av
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`else
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`ifdef as
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`else
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reg aw [];
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reg [31:0] ax [031];
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`endif
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`endif
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reg [31:0] ay= aw;
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wire [31:0] az = ax[at]
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;
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`ifdef x
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`else
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wire [31:0] ba = az
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`endif
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;
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wire [31:0] bb = az;
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wire [31:0] bc = `ifdef d
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`else
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bb;
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`endif
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always@(posedge CLK)
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begin
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`ifdef ag
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`else
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ar <= 0;
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ax[DPTR] <=
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4;
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`endif
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end
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assign DATAO = ba;
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assign aa = au;
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`ifdef x
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`else
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assign m = LCC;
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assign l = aq;
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assign ab = 'b1111;
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assign IADDR = ay;
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`endif
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assign y = ar;
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assign DEBUG = { an, ar, aq, LCC };
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endmodule
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