mirror of
https://github.com/sehugg/8bitworkshop.git
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made WorkerOutput/VerilogOutput type more specific; FILE__filename_ext define for mcpp
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parent
43e33f143c
commit
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18
src/ui.ts
18
src/ui.ts
@ -5,7 +5,7 @@
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import $ = require("jquery");
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import $ = require("jquery");
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import * as bootstrap from "bootstrap";
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import * as bootstrap from "bootstrap";
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import { CodeProject } from "./project";
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import { CodeProject } from "./project";
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import { WorkerResult, SourceFile, WorkerError } from "./workertypes";
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import { WorkerResult, WorkerOutput, VerilogOutput, SourceFile, WorkerError } from "./workertypes";
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import { ProjectWindows } from "./windows";
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import { ProjectWindows } from "./windows";
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import { Platform, Preset, DebugSymbols } from "./baseplatform";
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import { Platform, Preset, DebugSymbols } from "./baseplatform";
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import { PLATFORMS } from "./emu";
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import { PLATFORMS } from "./emu";
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@ -57,7 +57,7 @@ function newWorker() : Worker {
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var userPaused : boolean; // did user explicitly pause?
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var userPaused : boolean; // did user explicitly pause?
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var current_output; // current ROM
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var current_output : WorkerOutput; // current ROM
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var current_preset_entry : Preset; // current preset object (if selected)
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var current_preset_entry : Preset; // current preset object (if selected)
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var main_file_id : string; // main file ID
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var main_file_id : string; // main file ID
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var store; // persistent store
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var store; // persistent store
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@ -324,13 +324,17 @@ function _shareEmbedLink(e) {
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alert("Please fix errors before sharing.");
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alert("Please fix errors before sharing.");
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return true;
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return true;
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}
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}
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if (!(current_output instanceof Uint8Array)) {
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alert("Can't share a Verilog executable yet. (It's not actually a ROM...)");
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return true;
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}
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loadScript('lib/clipboard.min.js', () => {
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loadScript('lib/clipboard.min.js', () => {
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var ClipboardJS = exports['ClipboardJS'];
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var ClipboardJS = exports['ClipboardJS'];
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new ClipboardJS(".btn");
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new ClipboardJS(".btn");
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});
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});
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loadScript('lib/liblzg.js', () => {
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loadScript('lib/liblzg.js', () => {
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// TODO: Module is bad var name (conflicts with MAME)
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// TODO: Module is bad var name (conflicts with MAME)
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var lzgrom = compressLZG( window['Module'], current_output );
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var lzgrom = compressLZG( window['Module'], Array.from(<Uint8Array>current_output) );
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window['Module'] = null; // so we load it again next time
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window['Module'] = null; // so we load it again next time
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var lzgb64 = btoa(byteArrayToString(lzgrom));
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var lzgb64 = btoa(byteArrayToString(lzgrom));
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var embed = {
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var embed = {
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@ -415,12 +419,12 @@ function _downloadROMImage(e) {
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alert("Please finish compiling with no errors before downloading ROM.");
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alert("Please finish compiling with no errors before downloading ROM.");
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return true;
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return true;
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}
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}
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if (current_output.code) { // TODO
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if (current_output instanceof Uint8Array) {
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var blob = new Blob([current_output.code], {type: "text/plain"});
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saveAs(blob, getCurrentMainFilename()+".js");
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} else {
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var blob = new Blob([current_output], {type: "application/octet-stream"});
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var blob = new Blob([current_output], {type: "application/octet-stream"});
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saveAs(blob, getCurrentMainFilename()+".rom");
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saveAs(blob, getCurrentMainFilename()+".rom");
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} else {
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var blob = new Blob([(<VerilogOutput>current_output).code], {type: "text/plain"});
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saveAs(blob, getCurrentMainFilename()+".js");
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}
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}
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}
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}
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@ -1162,6 +1162,10 @@ function compileSDCC(step:BuildStep) {
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};
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};
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}
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}
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function makeCPPSafe(s:string) : string {
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return s.replace(/[^A-Za-z0-9_]/g,'_');
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}
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function preprocessMCPP(step:BuildStep) {
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function preprocessMCPP(step:BuildStep) {
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load("mcpp");
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load("mcpp");
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var platform = step.platform;
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var platform = step.platform;
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@ -1182,8 +1186,9 @@ function preprocessMCPP(step:BuildStep) {
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// TODO: make configurable by other compilers
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// TODO: make configurable by other compilers
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var args = [
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var args = [
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"-D", "__8BITWORKSHOP__",
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"-D", "__8BITWORKSHOP__",
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"-D", platform.toUpperCase().replace(/[-.]/g,'_'),
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"-D", "__SDCC_z80",
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"-D", "__SDCC_z80",
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"-D", makeCPPSafe(platform.toUpperCase()),
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"-D", "FILE__" + makeCPPSafe(step.path+""),
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"-I", "/share/include",
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"-I", "/share/include",
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"-Q",
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"-Q",
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step.path, "main.i"];
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step.path, "main.i"];
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@ -83,8 +83,10 @@ export interface CodeListing {
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export type CodeListingMap = {[path:string]:CodeListing};
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export type CodeListingMap = {[path:string]:CodeListing};
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// TODO
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// TODO
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export type WorkerOutput = Uint8Array |
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export type VerilogOutput =
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{program_rom_variable:string, program_rom:Uint8Array, code:{}, name:string, ports:any[], signals:any[]};
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{program_rom_variable:string, program_rom:Uint8Array, code:string, name:string, ports:any[], signals:any[]};
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export type WorkerOutput = Uint8Array | VerilogOutput;
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export interface WorkerResult {
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export interface WorkerResult {
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output:WorkerOutput,
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output:WorkerOutput,
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