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This commit is contained in:
Steven Hugg 2018-03-01 20:17:37 -06:00
parent db005dc98e
commit 725770ea3b
2 changed files with 15 additions and 9 deletions
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3
presets/verilog/cpu_platform.v
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@ -72,7 +72,6 @@ module cpu_platform(clk, reset, hsync, vsync, rgb);
.reset(reset),
.hpos(hpos),
.vpos(vpos),
.display_on(display_on),
.ram_addr(tile_ram_addr),
.ram_read(ram_read),
.ram_busy(tile_reading),
@ -171,7 +170,7 @@ ClearLoop:
ClearSprites:
mov bx,@$7f00
mov ax,#0
mov cx,#$80
mov cx,#$40
ClearSLoop:
mov ax,[bx]
add ax,@$101

21
presets/verilog/tile_renderer.v
View File

@ -11,6 +11,10 @@ module tile_renderer(clk, reset, hpos, vpos,
input [8:0] hpos;
input [8:0] vpos;
output [3:0] rgb;
// start loading cells from RAM at this hpos value
// first column read will be ((HLOAD-2) % 32)
parameter HLOAD = 272;
output reg [15:0] ram_addr;
input [15:0] ram_read;
@ -45,20 +49,23 @@ module tile_renderer(clk, reset, hpos, vpos,
// time to read a row?
if (vpos[2:0] == 7) begin
// read row_base from page table (2 bytes)
case (hpos[7:0])
185: ram_busy <= 1;
190: ram_addr <= {page_base, 3'b000, row};
192: row_base <= ram_read;
192+32: begin
case (hpos)
// assert busy 5 cycles before first RAM read
HLOAD-8: ram_busy <= 1;
// read page base for row
HLOAD-3: ram_addr <= {page_base, 3'b000, row};
HLOAD-1: row_base <= ram_read;
// deassert BUSY and increment row counter
HLOAD+34: begin
ram_busy <= 0;
row <= row + 1;
end
endcase
// load row of tile data from RAM
// (last two twice)
if (hpos >= 192 && hpos < 192+34) begin
if (hpos >= HLOAD && hpos < HLOAD+34) begin
ram_addr <= row_base + 16'(hpos[4:0]);
row_buffer[hpos[4:0]-2] <= ram_read;
row_buffer[hpos[4:0] - 5'd2] <= ram_read;
end
end
// latch character data