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https://github.com/sehugg/8bitworkshop.git
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new presets
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@ -72,7 +72,6 @@ module cpu_platform(clk, reset, hsync, vsync, rgb);
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.reset(reset),
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.reset(reset),
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.hpos(hpos),
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.hpos(hpos),
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.vpos(vpos),
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.vpos(vpos),
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.display_on(display_on),
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.ram_addr(tile_ram_addr),
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.ram_addr(tile_ram_addr),
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.ram_read(ram_read),
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.ram_read(ram_read),
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.ram_busy(tile_reading),
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.ram_busy(tile_reading),
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@ -171,7 +170,7 @@ ClearLoop:
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ClearSprites:
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ClearSprites:
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mov bx,@$7f00
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mov bx,@$7f00
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mov ax,#0
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mov ax,#0
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mov cx,#$80
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mov cx,#$40
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ClearSLoop:
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ClearSLoop:
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mov ax,[bx]
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mov ax,[bx]
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add ax,@$101
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add ax,@$101
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@ -12,6 +12,10 @@ module tile_renderer(clk, reset, hpos, vpos,
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input [8:0] vpos;
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input [8:0] vpos;
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output [3:0] rgb;
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output [3:0] rgb;
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// start loading cells from RAM at this hpos value
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// first column read will be ((HLOAD-2) % 32)
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parameter HLOAD = 272;
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output reg [15:0] ram_addr;
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output reg [15:0] ram_addr;
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input [15:0] ram_read;
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input [15:0] ram_read;
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output reg ram_busy;
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output reg ram_busy;
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@ -45,20 +49,23 @@ module tile_renderer(clk, reset, hpos, vpos,
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// time to read a row?
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// time to read a row?
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if (vpos[2:0] == 7) begin
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if (vpos[2:0] == 7) begin
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// read row_base from page table (2 bytes)
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// read row_base from page table (2 bytes)
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case (hpos[7:0])
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case (hpos)
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185: ram_busy <= 1;
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// assert busy 5 cycles before first RAM read
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190: ram_addr <= {page_base, 3'b000, row};
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HLOAD-8: ram_busy <= 1;
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192: row_base <= ram_read;
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// read page base for row
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192+32: begin
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HLOAD-3: ram_addr <= {page_base, 3'b000, row};
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HLOAD-1: row_base <= ram_read;
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// deassert BUSY and increment row counter
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HLOAD+34: begin
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ram_busy <= 0;
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ram_busy <= 0;
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row <= row + 1;
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row <= row + 1;
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end
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end
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endcase
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endcase
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// load row of tile data from RAM
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// load row of tile data from RAM
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// (last two twice)
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// (last two twice)
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if (hpos >= 192 && hpos < 192+34) begin
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if (hpos >= HLOAD && hpos < HLOAD+34) begin
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ram_addr <= row_base + 16'(hpos[4:0]);
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ram_addr <= row_base + 16'(hpos[4:0]);
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row_buffer[hpos[4:0]-2] <= ram_read;
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row_buffer[hpos[4:0] - 5'd2] <= ram_read;
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end
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end
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end
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end
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// latch character data
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// latch character data
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