6502/8bitworkshop
1
0
Fork 0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2025-04-02 07:29:52 +00:00
Code Issues Projects Releases Wiki Activity

started adding verilog regress tests

Browse Source
This commit is contained in:
Steven Hugg 2017-11-22 09:42:07 -05:00
parent e2a9876571
commit 73e908256e
28 changed files with 2879 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/platform/verilog.js
View File

@ -27,7 +27,12 @@ var VERILOG_KEYCODE_MAP = makeKeycodeMap([
[Keys.VK_7, 0, 0x400],
]);
var VL_UL = function(x) { return x; }
var vl_finished = false;
var vl_stopped = false;
var VL_UL = function(x) { return x|0; }
var VL_ULL = function(x) { return x|0; }
var VL_TIME_Q = function() { return (new Date().getTime())|0; }
/// Return true if data[bit] set
var VL_BITISSET_I = this.VL_BITISSET_I = function(data,bit) { return (data & (VL_UL(1)<<VL_BITBIT_I(bit))); }
@ -56,12 +61,26 @@ var VERILOG_KEYCODE_MAP = makeKeycodeMap([
var VL_GTES_III = this.VL_GTES_III = function(x,lbits,y,lhs,rhs) {
return VL_EXTENDS_II(x,lbits,lhs) >= VL_EXTENDS_II(x,lbits,rhs); }
var VL_MODDIV_III = this.VL_MODDIV_III = function(lbits,lhs,rhs) {
return (((rhs)==0)?0:(lhs)%(rhs)); }
var VL_WRITEF = this.VL_WRITEF = console.log; // TODO: $write
var vl_finish = this.vl_finish = function(filename,lineno,hier) {
console.log("Finished at " + filename + ":" + lineno);
vl_finished = true;
}
var vl_stop = this.vl_stop = function(filename,lineno,hier) {
console.log("Finished at " + filename + ":" + lineno);
vl_stopped = true;
}
var VL_RAND_RESET_I = this.VL_RAND_RESET_I = function(bits) { return Math.floor(Math.random() * (1<<bits)); }
//
function VerilatorBase() {
var VL_RAND_RESET_I = this.VL_RAND_RESET_I = function(bits) { return Math.floor(Math.random() * (1<<bits)); }
//
function vl_fatal(msg) {
@ -298,7 +317,7 @@ var VerilogPlatform = function(mainElement, options) {
});
}
function printErrorCodeContext(e, code) {
this.printErrorCodeContext = function(e, code) {
if (e.lineNumber && e.message) {
var lines = code.split('\n');
var s = e.message + '\n';
@ -316,7 +335,7 @@ var VerilogPlatform = function(mainElement, options) {
try {
mod = new Function('base', output.code);
} catch (e) {
printErrorCodeContext(e, output.code);
this.printErrorCodeContext(e, output.code);
throw e;
}
var base = new VerilatorBase();
@ -345,6 +364,9 @@ var VerilogPlatform = function(mainElement, options) {
this.reset = function() {
gen.reset2();
}
this.tick = function() {
gen.tick2();
}
this.getToolForFilename = function(fn) {
return "verilator";
}

12
src/worker/verilator2js.js
View File

@ -2,7 +2,7 @@
var moduleName, symsName;
function parseDecls(text, arr, name, bin, bout) {
var re = new RegExp(name + "(\\d+)[(](\\w+),(\\d+),(\\d+)[)]", 'gm');
var re = new RegExp(name + "(\\d*)[(](\\w+),(\\d+),(\\d+)[)]", 'gm');
var m;
while ((m = re.exec(text))) {
arr.push({
@ -12,7 +12,7 @@ function parseDecls(text, arr, name, bin, bout) {
ofs:parseInt(m[4]),
});
}
re = new RegExp(name + "(\\d+)[(](\\w+)\\[(\\d+)\\],(\\d+),(\\d+)[)]", 'gm');
re = new RegExp(name + "(\\d*)[(](\\w+)\\[(\\d+)\\],(\\d+),(\\d+)[)]", 'gm');
var m;
while ((m = re.exec(text))) {
arr.push({
@ -23,7 +23,7 @@ function parseDecls(text, arr, name, bin, bout) {
ofs:parseInt(m[5]),
});
}
re = new RegExp(name + "(\\d+)[(](\\w+)\\[(\\d+)\\]\\[(\\d+)\\],(\\d+),(\\d+)[)]", 'gm');
re = new RegExp(name + "(\\d*)[(](\\w+)\\[(\\d+)\\]\\[(\\d+)\\],(\\d+),(\\d+)[)]", 'gm');
var m;
while ((m = re.exec(text))) {
arr.push({
@ -39,7 +39,6 @@ function parseDecls(text, arr, name, bin, bout) {
function buildModule(o) {
var m = '"use strict";\n';
m += '\tvar self = this;\n';
m += '\tvar VL_RAND_RESET_I = base.VL_RAND_RESET_I;\n';
for (var i=0; i<o.ports.length; i++) {
m += "\tself." + o.ports[i].name + ";\n";
}
@ -68,7 +67,7 @@ function translateFunction(text) {
text = text.replace(symsName + "* __restrict ", "");
text = text.replace(moduleName + "* __restrict vlTOPp VL_ATTR_UNUSED", "var vlTOPp");
text = text.replace(/VL_DEBUG_IF/g,"//VL_DEBUG_IF");
text = text.replace(/VL_SIG\d+[(](\w+),(\d+),(\d+)[)]/g, 'var $1');
text = text.replace(/VL_SIG(\d*)[(](\w+),(\d+),(\d+)[)]/g, 'var $2');
text = text.replace(/\b->\b/g, ".");
text = text.replace('VL_INLINE_OPT', '');
text = text.replace(/[(]IData[)]/g, '');
@ -77,7 +76,8 @@ function translateFunction(text) {
text = text.replace(/\bQData /g, 'var ');
text = text.replace(/\bbool /g, '');
text = text.replace(/\bint /g, 'var ');
text = text.replace(/(\w+ = VL_RAND_RESET_I)/g, 'self.$1');
text = text.replace(/(\w+ = VL_RAND_RESET_)/g, 'self.$1'); // TODO?
text = text.replace(/^\s*(\w+ = \d+;)/gm, 'self.$1'); // TODO?
//text = text.replace(/(\w+\[\w+\] = VL_RAND_RESET_I)/g, 'self.$1');
text = text.replace(/^#/gm, '//#');
text = text.replace(/VL_LIKELY/g, '!!');

85
test/cli/testverilog.js Normal file
View File

@ -0,0 +1,85 @@
var assert = require('assert');
var fs = require('fs');
var wtu = require('./workertestutils.js');
includeInThisContext('src/emu.js');
includeInThisContext('src/platform/verilog.js');
function loadPlatform(msg) {
var platform = new VerilogPlatform();
try {
platform.loadROM("ROM", msg.output);
vl_finished = vl_stopped = false;
for (var i=0; i<100 && !(vl_finished||vl_stopped); i++)
platform.tick();
} catch (e) {
//platform.printErrorCodeContext(e, msg.output.code);
console.log(msg.intermediate.listing);
console.log(msg.output.code);
console.log(e);
throw e;
}
return platform;
}
function compileVerilator(code, callback, nerrors) {
global.postMessage = function(msg) {
if (msg.errors && msg.errors.length) {
console.log(msg.errors);
assert.equal(nerrors||0, msg.errors.length, "errors");
} else {
assert.equal(nerrors||0, 0, "errors");
loadPlatform(msg);
}
callback(null, msg);
};
global.onmessage({
data:{code:code, platform:'verilog', tool:'verilator'}
});
}
function testVerilator(filename, disables, nerrors) {
it('should translate '+filename, function(done) {
var csource = ab2str(fs.readFileSync(filename));
for (var i=0; i<(disables||[]).length; i++)
csource = "/* verilator lint_off " + disables[i] + " */\n" + csource;
compileVerilator(csource, done, nerrors||0);
});
}
describe('Verilog Worker', function() {
testVerilator('test/cli/verilog/t_mem.v');
testVerilator('test/cli/verilog/t_alw_combdly.v');
testVerilator('test/cli/verilog/t_alw_dly.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_alw_split.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_alw_splitord.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_array_compare.v');
testVerilator('test/cli/verilog/t_math_arith.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_math_const.v', ['BLKSEQ']);
//testVerilator('test/cli/verilog/t_math_div.v');
testVerilator('test/cli/verilog/t_math_div0.v');
testVerilator('test/cli/verilog/t_clk_powerdn.v', ['BLKSEQ','SYNCASYNCNET']);
//testVerilator('test/cli/verilog/t_clk_latchgate.v', ['BLKSEQ']);
//testVerilator('test/cli/verilog/t_clk_latch.v');
testVerilator('test/cli/verilog/t_clk_gen.v', ['BLKSEQ']);
//testVerilator('test/cli/verilog/t_clk_gater.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_clk_first.v', ['UNDRIVEN','SYNCASYNCNET']);
testVerilator('test/cli/verilog/t_clk_dsp.v');
testVerilator('test/cli/verilog/t_clk_dpulse.v');
testVerilator('test/cli/verilog/t_clk_condflop_nord.v');
testVerilator('test/cli/verilog/t_clk_condflop.v', ['BLKSEQ']);
testVerilator('test/cli/verilog/t_clk_2in.v', ['BLKSEQ']);
testVerilator('presets/verilog/hvsync_generator.v');
/*
it('should compile verilog example', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/hvsync_generator.v'));
compileVerilator(csource, done);
});
*/
});

64
test/cli/testworker.js
View File

@ -1,63 +1,7 @@
var assert = require('assert');
var fs = require('fs');
var vm = require('vm');
var worker = {};
var includeInThisContext = function(path) {
var code = fs.readFileSync(path);
vm.runInThisContext(code, path);
};
global.importScripts = function(path) {
includeInThisContext('src/worker/'+path);
}
function Blob(blob) {
this.size = blob.length;
this.length = blob.length;
this.slice = function(a,b) {
var data = blob.slice(a,b);
var b = new Blob(data);
//console.log(a, b, data.length, data.slice(0,64));
//console.log(new Error().stack);
return b;
}
this.asArrayBuffer = function() {
var buf = new ArrayBuffer(blob.length);
var arr = new Uint8Array(buf);
for (var i=0; i<blob.length; i++)
arr[i] = blob[i].charCodeAt(0);
return arr;
}
}
global.XMLHttpRequest = function() {
this.open = function(a,b,c) {
if (this.responseType == 'json') {
var txt = fs.readFileSync('src/worker/'+b);
this.response = JSON.parse(txt);
} else if (this.responseType == 'blob') {
var data = fs.readFileSync('src/worker/'+b, {encoding:'binary'});
//var buf = new ArrayBuffer(data.length);
//var blob = new Uint8Array(buf);
//blob.set(data);
this.response = new Blob(data);
}
}
this.send = function() { }
}
global.FileReaderSync = function() {
this.readAsArrayBuffer = function(blob) {
return blob.asArrayBuffer();
}
}
global.onmessage = null;
global.postMessage = null;
includeInThisContext("src/worker/workermain.js");
var wtu = require('./workertestutils.js');
global.onmessage({data:{preload:'cc65'}});
global.onmessage({data:{preload:'sdcc'}});
@ -81,10 +25,6 @@ function compile(tool, code, platform, callback, outlen, nlines, nerrors) {
});
}
function ab2str(buf) {
return String.fromCharCode.apply(null, new Uint16Array(buf));
}
describe('Worker', function() {
it('should assemble DASM', function(done) {
compile('dasm', '\tprocessor 6502\n\torg $f000\nfoo lda #0\n', 'vcs', done, 2, 1);
@ -161,7 +101,7 @@ describe('Worker', function() {
});
it('should compile verilog example', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/lfsr.v'));
compile('verilator', csource, 'verilog', done, 3731, 0, 0);
compile('verilator', csource, 'verilog', done, 3686, 0, 0);
});
it('should NOT compile SDCC', function(done) {
compile('sdcc', 'foobar', 'mw8080bw', done, 0, 0, 1);

60
test/cli/verilog/t_alw_combdly.v Normal file
View File

@ -0,0 +1,60 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g, h;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
c <= a | b;
// verilator lint_on COMBDLY
end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
parameter CONSTANT = 1;
always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
f = e;
end
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
always @ ({CONSTANT, g}) begin // bug745
h = g;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
a <= 32'hfeed0000;
b <= 32'h0000face;
end
if (cyc==2) begin
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
if (h != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

63
test/cli/verilog/t_alw_dly.v Normal file
View File

@ -0,0 +1,63 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

131
test/cli/verilog/t_alw_split.v Normal file
View File

@ -0,0 +1,131 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] a_split_1, a_split_2;
always @ (/*AS*/m_din) begin
a_split_1 = m_din;
a_split_2 = m_din;
end
// OK
reg [15:0] b_split_1, b_split_2;
always @ (/*AS*/m_din) begin
b_split_1 = m_din;
b_split_2 = b_split_1;
end
// Not OK
reg [15:0] c_split_1, c_split_2;
always @ (/*AS*/m_din) begin
c_split_1 = m_din;
c_split_2 = c_split_1;
c_split_1 = ~m_din;
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
// Not OK
always @ (posedge clk) begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
// Not Ok
reg [15:0] l_split_1, l_split_2;
always @ (posedge clk) begin
l_split_2 <= l_split_1;
l_split_1 <= l_split_2 | m_din;
end
// OK
reg [15:0] z_split_1, z_split_2;
always @ (posedge clk) begin
z_split_1 <= 0;
z_split_1 <= ~m_din;
end
always @ (posedge clk) begin
z_split_2 <= 0;
z_split_2 <= z_split_1;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
//$write(" A %x %x\n", a_split_1, a_split_2);
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop;
if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop;
if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop;
if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

151
test/cli/verilog/t_alw_splitord.v Normal file
View File

@ -0,0 +1,151 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c_split_1 <= 16'h0;
c_split_2 <= 16'h0;
c_split_3 <= 16'h0;
c_split_4 <= 0;
c_split_5 <= 0;
// End of automatics
end
else begin
c_split_1 <= m_din;
c_split_2 <= c_split_1;
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
if (cyc==1) begin
c_split_4 <= 16'h4;
c_split_5 <= 16'h5;
end
else begin
c_split_4 <= c_split_3;
c_split_5 <= c_split_4;
end
end
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
d_split_1 <= 16'h0;
d_split_2 <= 16'h0;
// End of automatics
end
else begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
end
// Not OK
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
// End of automatics
end
else begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
e_split_1 = 16'h0;
e_split_2 = 16'h0;
// End of automatics
end
else begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
if (cyc==0) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_split_1 = 16'h0;
f_split_2 = 16'h0;
// End of automatics
end
else begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
m_din <= 16'he44e;
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
end
if (cyc==8) begin
m_din <= 16'he55e;
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

58
test/cli/verilog/t_array_compare.v Normal file
View File

@ -0,0 +1,58 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Andrew Bardsley.
// bug1071
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];
reg [3:0] array_3 [3:1];
reg [3:0] elem;
reg array_1_ne_array_2;
reg array_1_eq_array_2;
reg array_1_ne_array_3;
reg array_1_eq_array_3;
initial begin
array_1[0] = 4'b1000;
array_1[1] = 4'b1000;
array_1[2] = 4'b1000;
array_2[0] = 4'b1000;
array_2[1] = 4'b1000;
array_2[2] = 4'b1000;
array_3[1] = 4'b1000;
array_3[2] = 4'b0100;
array_3[3] = 4'b0100;
// Comparisons only compare elements 0
array_1_ne_array_2 = array_1 != array_2; // 0
array_1_eq_array_2 = array_1 == array_2; // 0
array_1_ne_array_3 = array_1 != array_3; // 1
array_1_eq_array_3 = array_1 == array_3; // 1
`ifdef TEST_VERBOSE
$write("array_1_ne_array2==%0d\n", array_1_ne_array_2);
$write("array_1_ne_array3==%0d\n", array_1_ne_array_3);
`endif
if (array_1_ne_array_2 !== 0) $stop;
if (array_1_eq_array_2 !== 1) $stop;
if (array_1_ne_array_3 !== 1) $stop;
if (array_1_eq_array_3 !== 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

162
test/cli/verilog/t_clk_2in.v Normal file
View File

@ -0,0 +1,162 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
`ifndef VERILATOR
module t;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg c0; // To t2 of t2.v
reg c1; // To t2 of t2.v
reg check; // To t2 of t2.v
reg [1:0] clks; // To t2 of t2.v
// End of automatics
t2 t2 (/*AUTOINST*/
// Inputs
.clks (clks[1:0]),
.c0 (c0),
.c1 (c1),
.check (check));
task clockit (input v1, v0);
c1 = v1;
c0 = v0;
clks[1] = v1;
clks[0] = v0;
`ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif
#1;
endtask
initial begin
check = '0;
c0 = '0;
c1 = '0;
clks = '0;
#1
t2.clear();
#10;
for (int i=0; i<2; i++) begin
clockit(0, 0);
clockit(0, 0);
clockit(0, 1);
clockit(1, 1);
clockit(0, 0);
clockit(1, 1);
clockit(1, 0);
clockit(0, 0);
clockit(1, 0);
clockit(0, 1);
clockit(0, 0);
end
check = 1;
clockit(0, 0);
end
endmodule
`endif
`ifdef VERILATOR
`define t2 t
`else
`define t2 t2
`endif
module `t2 (
input [1:0] clks,
input c0,
input c1,
input check
);
`ifdef T_CLK_2IN_VEC
wire clk0 = clks[0];
wire clk1 = clks[1];
`else
wire clk0 = c0;
wire clk1 = c1;
`endif
integer p0 = 0;
integer p1 = 0;
integer p01 = 0;
integer n0 = 0;
integer n1 = 0;
integer n01 = 0;
integer vp = 0;
integer vn = 0;
integer vpn = 0;
task clear;
`ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif
p0 = 0;
p1 = 0;
p01 = 0;
n0 = 0;
n1 = 0;
n01 = 0;
vp = 0;
vn = 0;
vpn = 0;
endtask
`define display_counts(text) begin \
$write("[%0t] ",$time); \
`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
$write(text); \
$write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \
end
always @ (posedge clk0) begin
p0 = p0 + 1; // Want blocking, so don't miss clock counts
`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
end
always @ (posedge clk1) begin
p1 = p1 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
end
always @ (posedge clk0 or posedge clk1) begin
p01 = p01 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
end
always @ (negedge clk0) begin
n0 = n0 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
end
always @ (negedge clk1) begin
n1 = n1 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
end
always @ (negedge clk0 or negedge clk1) begin
n01 = n01 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
end
`ifndef VERILATOR
always @ (posedge clks) begin
vp = vp + 1;
`ifdef TEST_VERBOSE `display_counts("pos vec"); `endif
end
always @ (negedge clks) begin
vn = vn + 1;
`ifdef TEST_VERBOSE `display_counts("neg vec"); `endif
end
always @ (posedge clks or negedge clks) begin
vpn = vpn + 1;
`ifdef TEST_VERBOSE `display_counts("or vec"); `endif
end
`endif
always @ (posedge check) begin
if (p0!=6) $stop;
if (p1!=6) $stop;
if (p01!=10) $stop;
if (n0!=6) $stop;
if (n1!=6) $stop;
if (n01!=10) $stop;
`ifndef VERILATOR
if (vp!=6) $stop;
if (vn!=6) $stop;
if (vpn!=12) $stop;
`endif
$write("*-* All Finished *-*\n");
end
endmodule

124
test/cli/verilog/t_clk_condflop.v Normal file
View File

@ -0,0 +1,124 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule

124
test/cli/verilog/t_clk_condflop_nord.v Normal file
View File

@ -0,0 +1,124 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule

46
test/cli/verilog/t_clk_dpulse.v Normal file
View File

@ -0,0 +1,46 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg genclk;
// verilator lint_off MULTIDRIVEN
reg [7:0] set_both;
// verilator lint_on MULTIDRIVEN
wire genthiscyc = ( (cyc % 2) == 1 );
always @ (posedge clk) begin
cyc <= cyc + 8'h1;
genclk <= genthiscyc;
set_both <= cyc;
$write ("SB set_both %x <= cyc %x\n", set_both, cyc);
if (genthiscyc) begin
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
end
else begin
if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @ (posedge genclk) begin
set_both <= ~ set_both;
$write ("SB set_both %x <= cyc %x\n", set_both, ~cyc);
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
end
endmodule

175
test/cli/verilog/t_clk_dsp.v Normal file
View File

@ -0,0 +1,175 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg [7:0] padd;
reg dsp_ph1, dsp_ph2, dsp_reset;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] out; // From dspchip of t_dspchip.v
// End of automatics
t_dspchip dspchip (/*AUTOINST*/
// Outputs
.out (out[7:0]),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
always @ (posedge clk) begin
$write("cyc %d\n",cyc);
if (cyc == 8'd0) begin
cyc <= 8'd1;
dsp_reset <= 0; // Need a posedge
padd <= 0;
end
else if (cyc == 8'd20) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
cyc <= cyc + 8'd1;
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
dsp_reset <= (cyc == 8'd1);
padd <= cyc;
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
case (cyc)
default: $stop;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: ;
8'd05: ;
8'd06: ;
8'd07: ;
8'd08: ;
8'd09: if (out!==8'h04) $stop;
8'd10: if (out!==8'h04) $stop;
8'd11: if (out!==8'h08) $stop;
8'd12: if (out!==8'h08) $stop;
8'd13: if (out!==8'h00) $stop;
8'd14: if (out!==8'h00) $stop;
8'd15: if (out!==8'h00) $stop;
8'd16: if (out!==8'h00) $stop;
8'd17: if (out!==8'h0c) $stop;
8'd18: if (out!==8'h0c) $stop;
8'd19: if (out!==8'h10) $stop;
endcase
end
end
endmodule
module t_dspchip (/*AUTOARG*/
// Outputs
out,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, padd
);
input dsp_ph1, dsp_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out;
wire dsp_ph1, dsp_ph2;
wire [7:0] out;
wire pla_ph1, pla_ph2;
wire out1_r;
wire [7:0] out2_r, padd;
wire clk_en;
t_dspcore t_dspcore (/*AUTOINST*/
// Outputs
.out1_r (out1_r),
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.clk_en (clk_en));
t_dsppla t_dsppla (/*AUTOINST*/
// Outputs
.out2_r (out2_r[7:0]),
// Inputs
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
assign out = out1_r ? 8'h00 : out2_r;
assign clk_en = 1'b1;
endmodule
module t_dspcore (/*AUTOARG*/
// Outputs
out1_r, pla_ph1, pla_ph2,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, clk_en
);
input dsp_ph1, dsp_ph2, dsp_reset;
input clk_en;
output out1_r, pla_ph1, pla_ph2;
wire dsp_ph1, dsp_ph2, dsp_reset;
wire pla_ph1, pla_ph2;
reg out1_r;
always @(posedge dsp_ph1 or posedge dsp_reset) begin
if (dsp_reset)
out1_r <= 1'h0;
else
out1_r <= ~out1_r;
end
assign pla_ph1 = dsp_ph1;
assign pla_ph2 = dsp_ph2 & clk_en;
endmodule
module t_dsppla (/*AUTOARG*/
// Outputs
out2_r,
// Inputs
pla_ph1, pla_ph2, dsp_reset, padd
);
input pla_ph1, pla_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out2_r;
wire pla_ph1, pla_ph2, dsp_reset;
wire [7:0] padd;
reg [7:0] out2_r;
reg [7:0] latched_r;
always @(posedge pla_ph1 or posedge dsp_reset) begin
if (dsp_reset)
latched_r <= 8'h00;
else
latched_r <= padd;
end
always @(posedge pla_ph2 or posedge dsp_reset) begin
if (dsp_reset)
out2_r <= 8'h00;
else
out2_r <= latched_r;
end
endmodule

202
test/cli/verilog/t_clk_first.v Normal file
View File

@ -0,0 +1,202 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
reg reset_l;
int cyc;
initial reset_l = 0;
always @ (posedge clk) begin
if (cyc==0) reset_l <= 1'b1;
else if (cyc==1) reset_l <= 1'b0;
else if (cyc==10) reset_l <= 1'b1;
end
t_clk t (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk (/*AUTOARG*/
// Inputs
clk, fastclk, reset_l
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input reset_l;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK1 %x\n", $time, reset_l);
`endif
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n",$time);
`endif
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
`endif
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
`endif
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK4 %x\n", $time, reset_l);
`endif
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk_flop (/*AUTOARG*/
// Outputs
q, q2,
// Inputs
clk, clk2, a
);
parameter WIDTH=8;
input clk;
input clk2;
input [(WIDTH-1):0] a;
output [(WIDTH-1):0] q;
output [(WIDTH-1):0] q2;
reg [(WIDTH-1):0] q;
reg [(WIDTH-1):0] q2;
always @ (posedge clk) q<=a;
always @ (posedge clk2) q2<=a;
endmodule
module t_clk_two (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
// verilator lint_off GENCLK
reg clk2;
// verilator lint_on GENCLK
reg [31:0] count;
t_clk_twob tb (.*);
wire reset_h = ~reset_l;
always @ (posedge fastclk) begin
if (reset_h) clk2 <= 0;
else clk2 <= ~clk2;
end
always @ (posedge clk2) begin
if (reset_h) count <= 0;
else count <= count + 1;
end
endmodule
module t_clk_twob (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
always @ (posedge fastclk) begin
// Extra line coverage point, just to make sure coverage
// hierarchy under inlining lands properly
if (reset_l) ;
end
endmodule

159
test/cli/verilog/t_clk_gater.v Normal file
View File

@ -0,0 +1,159 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule

86
test/cli/verilog/t_clk_gen.v Normal file
View File

@ -0,0 +1,86 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg gendlyclk_r;
reg [31:0] gendlydata_r;
reg [31:0] dlydata_gr;
reg genblkclk;
reg [31:0] genblkdata;
reg [31:0] blkdata_gr;
wire [31:0] constwire = 32'h11;
reg [31:0] initwire;
integer i;
initial begin
for (i=0; i<10000; i=i+1) begin
initwire = 32'h2200;
end
end
wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire;
always @ (posedge clk) begin
gendlydata_r <= 32'h0011_0000;
gendlyclk_r <= 0;
// surefire lint_off SEQASS
genblkclk = 0;
genblkdata = 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
gendlyclk_r <= 1;
gendlydata_r <= 32'h00540000;
genblkclk = 1;
genblkdata = 32'hace;
$write("[%0t] Send pulse\n", $time);
end
if (cyc==3) begin
genblkdata = 32'hdce;
gendlydata_r <= 32'h00ff0000;
if (either != 32'h87542211) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// surefire lint_on SEQASS
end
always @ (posedge gendlyclk_r) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
dlydata_gr <= 32'h80000000;
// Delayed activity list will already be completed for gendlydata
// because genclk is from a delayed assignment.
// Thus we get the NEW not old value of gendlydata_r
if (gendlydata_r != 32'h00540000) $stop;
if (genblkdata != 32'hace) $stop;
end
end
always @ (posedge genblkclk) begin
if ($time>0) begin // Hack, don't split the block
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
blkdata_gr <= 32'h07000000;
// Clock from non-delayed assignment, we get old value of gendlydata_r
`ifdef verilator `else // V3.2 races... technically legal
if (gendlydata_r != 32'h00110000) $stop;
`endif
if (genblkdata != 32'hace) $stop;
end
end
endmodule

109
test/cli/verilog/t_clk_latch.v Normal file
View File

@ -0,0 +1,109 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc=0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule

178
test/cli/verilog/t_clk_latchgate.v Normal file
View File

@ -0,0 +1,178 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule

122
test/cli/verilog/t_clk_powerdn.v Normal file
View File

@ -0,0 +1,122 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg reset_l;
// verilator lint_off GENCLK
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
reg clkgate_e2r;
reg clkgate_e1r_l;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
clkgate_e1r_l <= ~1'b1;
end
else begin
clkgate_e1r_l <= ~clkgate_e2r;
end
end
reg clkgate_e1f;
always @(negedge clk) begin
// Yes, it's really a =
clkgate_e1f = ~clkgate_e1r_l | ~reset_l;
end
wire clkgated = clk & clkgate_e1f;
reg [31:0] countgated;
always @(posedge clkgated or negedge reset_l) begin
if (!reset_l) begin
countgated <= 32'h1000;
end
else begin
countgated <= countgated + 32'd1;
end
end
reg [31:0] count;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
count <= 32'h1000;
end
else begin
count <= count + 32'd1;
end
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated);
`endif
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
reset_l <= ~1'b0;
clkgate_e2r <= 1'b1;
end
8'd01: begin
reset_l <= ~1'b0;
end
8'd02: begin
end
8'd03: begin
reset_l <= ~1'b1; // Need a posedge
end
8'd04: begin
end
8'd05: begin
reset_l <= ~1'b0;
end
8'd09: begin
clkgate_e2r <= 1'b0;
end
8'd11: begin
clkgate_e2r <= 1'b1;
end
8'd20: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
8'd00: ;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop;
8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop;
8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop;
8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop;
8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop;
8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop;
8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop;
8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop;
8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop;
8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop;
8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop;
8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop;
8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop;
8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop;
default: $stop;
endcase
end
endmodule

123
test/cli/verilog/t_clk_vecgen1.v Normal file
View File

@ -0,0 +1,123 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif

160
test/cli/verilog/t_math_arith.v Normal file
View File

@ -0,0 +1,160 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
reg [9:0] mc;
reg [4:0] mr1;
reg [30:0] mr2;
reg [67:0] sh1;
reg [67:0] shq;
wire foo, bar; assign {foo,bar} = 2'b1_0;
// surefire lint_off STMINI
initial _ranit = 0;
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
wire zero = 1'b0;
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
// verilator lint_off WIDTH
localparam [3:0] bug764_p11 = 1'bx;
// verilator lint_on WIDTH
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
reg [63:0] m_data_pipe2_r;
reg [31:0] m_corr_data_w0, m_corr_data_w1;
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
end
endmodule

141
test/cli/verilog/t_math_const.v Normal file
View File

@ -0,0 +1,141 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
reg [31:0] v32 [2];
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\n",$time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
// Increments
v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop;
v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop;
v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop;
v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop;
v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop;
v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop;
v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop;
v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop;
v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop;
v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop;
v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

96
test/cli/verilog/t_math_div.v Normal file
View File

@ -0,0 +1,96 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

11
test/cli/verilog/t_math_div0.v Normal file
View File

@ -0,0 +1,11 @@
module t(y);
output [3:0] y;
// bug775
// verilator lint_off WIDTH
assign y = ((0/0) ? 1 : 2) % 0;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

145
test/cli/verilog/t_math_divw.v Normal file
View File

@ -0,0 +1,145 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
//============================================================
reg bad;
initial begin
bad=0;
c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888);
c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0);
c96(96'h0003, 96'h0002, 96'h0001, 96'h0001);
c96(96'h0003, 96'h0003, 96'h0001, 96'h0000);
c96(96'h0003, 96'h0004, 96'h0000, 96'h0003);
c96(96'h0000, 96'hffff, 96'h0000, 96'h0000);
c96(96'hffff, 96'h0001, 96'hffff, 96'h0000);
c96(96'hffff, 96'hffff, 96'h0001, 96'h0000);
c96(96'hffff, 96'h0003, 96'h5555, 96'h0000);
c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000);
c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000);
c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe);
c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70);
c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000);
c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000);
c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005);
c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000);
c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001);
c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000);
c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001);
c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899);
c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000);
c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff);
c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab);
c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff);
c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000);
c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000);
c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000);
c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000);
c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000);
c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000);
c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000);
c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000);
c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000);
c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000);
c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002);
c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff);
c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888);
if (bad) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
task c96;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
c96u( u, v, expq, expr);
c96s( u, v, expq, expr);
c96s(-u, v,-expq,-expr);
c96s( u,-v,-expq, expr);
c96s(-u,-v, expq,-expr);
endtask
task c96u;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
reg [95:0] gotq;
reg [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
task c96s;
input signed [95:0] u;
input signed [95:0] v;
input signed [95:0] expq;
input signed [95:0] expr;
reg signed [95:0] gotq;
reg signed [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
endmodule

68
test/cli/verilog/t_mem.v Normal file
View File

@ -0,0 +1,68 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule

65
test/cli/workertestutils.js Normal file
View File

@ -0,0 +1,65 @@
var assert = require('assert');
var fs = require('fs');
var vm = require('vm');
var worker = {};
global.includeInThisContext = function(path) {
var code = fs.readFileSync(path);
vm.runInThisContext(code, path);
};
global.importScripts = function(path) {
includeInThisContext('src/worker/'+path);
}
function Blob(blob) {
this.size = blob.length;
this.length = blob.length;
this.slice = function(a,b) {
var data = blob.slice(a,b);
var b = new Blob(data);
//console.log(a, b, data.length, data.slice(0,64));
//console.log(new Error().stack);
return b;
}
this.asArrayBuffer = function() {
var buf = new ArrayBuffer(blob.length);
var arr = new Uint8Array(buf);
for (var i=0; i<blob.length; i++)
arr[i] = blob[i].charCodeAt(0);
return arr;
}
}
global.XMLHttpRequest = function() {
this.open = function(a,b,c) {
if (this.responseType == 'json') {
var txt = fs.readFileSync('src/worker/'+b);
this.response = JSON.parse(txt);
} else if (this.responseType == 'blob') {
var data = fs.readFileSync('src/worker/'+b, {encoding:'binary'});
//var buf = new ArrayBuffer(data.length);
//var blob = new Uint8Array(buf);
//blob.set(data);
this.response = new Blob(data);
}
}
this.send = function() { }
}
global.FileReaderSync = function() {
this.readAsArrayBuffer = function(blob) {
return blob.asArrayBuffer();
}
}
global.onmessage = null;
global.postMessage = null;
includeInThisContext("src/worker/workermain.js");
global.ab2str = function(buf) {
return String.fromCharCode.apply(null, new Uint16Array(buf));
}