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verilog: send JSASM .json files to worker

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This commit is contained in:
Steven Hugg 2018-11-28 11:10:24 -05:00
parent 85b2241555
commit 79638ad01e
3 changed files with 27 additions and 15 deletions
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10
src/project.ts
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@ -70,11 +70,17 @@ export class CodeProject {
parseIncludeDependencies(text:string):string[] {
var files = [];
if (this.platform_id.startsWith('verilog')) {
var re = /^\s*(`include|[.]include)\s+"(.+?)"/gmi;
var re1 = /^\s*(`include|[.]include)\s+"(.+?)"/gmi;
var m;
while (m = re.exec(text)) {
while (m = re1.exec(text)) {
this.pushAllFiles(files, m[2]);
}
// include .arch (json) statements
var re2 = /^\s*([.]arch)\s+(\w+)/gmi;
var m;
while (m = re2.exec(text)) {
this.pushAllFiles(files, m[2]+".json");
}
} else {
// for .asm -- [.]include "file"
// for .c -- #include "file"

28
src/worker/workermain.ts
View File

@ -251,6 +251,10 @@ function wasChanged(entry:FileEntry) : boolean {
return entry.ts > buildstartseq;
}
function getWorkFileAsString(path:string) : string {
return workfs[path] && workfs[path].data as string; // TODO
}
function populateEntry(fs, path:string, entry:FileEntry) {
fs.writeFile(path, entry.data, {encoding:entry.encoding});
fs.utime(path, entry.ts, entry.ts);
@ -1122,7 +1126,7 @@ function compileSDCC(step:BuildStep) {
var FS = SDCC['FS'];
populateFiles(step, FS);
// load source file and preprocess
var code = workfs[step.path].data as string; // TODO
var code = getWorkFileAsString(step.path);
var preproc = preprocessMCPP(step);
if (preproc.errors) return preproc;
else code = preproc.code;
@ -1262,14 +1266,15 @@ function compileJSASM(asmcode:string, platform, options, is_inline) {
loadGen("worker/assembler");
var asm = new emglobal.exports.Assembler();
var includes = [];
asm.loadJSON = function(filename) {
// TODO: what if it comes from dependencies?
var path = '../../presets/' + platform + '/' + filename;
var xhr = new XMLHttpRequest();
xhr.responseType = 'json';
xhr.open("GET", path, false); // synchronous request
xhr.send(null);
return xhr.response;
asm.loadJSON = (filename:string) => {
var jsontext : string;
for (var dep of options.dependencies) {
if (dep.filename == filename)
jsontext = dep.data as string;
}
// TODO: var jsontext = getWorkFileAsString(filename) || getWorkFileAsString("local/"+filename);
if (!jsontext) throw "could not load " + filename;
return JSON.parse(jsontext);
};
asm.loadInclude = function(filename) {
if (!filename.startsWith('"') || !filename.endsWith('"'))
@ -1353,6 +1358,7 @@ function compileVerilator(step:BuildStep) {
var platform = step.platform || 'verilog';
var errors = [];
var asmlines = [];
// TODO? gatherFiles(step);
step.code = compileInlineASM(step.code, platform, step, errors, asmlines);
if (errors.length) {
return {errors:errors};
@ -1574,7 +1580,7 @@ function compileBatariBasic(step:BuildStep) {
var FS = BB['FS'];
populateFiles(step, FS);
// preprocess, pipe file to stdin
var code = workfs[step.path].data as string; // TODO
var code = getWorkFileAsString(step.path);
code = preprocessBatariBasic(code);
setupStdin(FS, code);
setupFS(FS, '2600basic');
@ -1636,7 +1642,7 @@ function translateShowdown(step:BuildStep) {
requireSpaceBeforeHeadingText:'true',
emoji:'true',
});
var code = workfs[step.path].data as string; // TODO
var code = getWorkFileAsString(step.path);
var html = converter.makeHtml(code);
delete emglobal['require'];
return {

4
test/cli/testworker.js
View File

@ -184,7 +184,7 @@ describe('Worker', function() {
});
it('should compile verilog inline assembler (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/racing_game_cpu.v'));
var dependfiles = ["hvsync_generator.v", "sprite_bitmap.v", "sprite_renderer.v", "cpu8.v"];
var dependfiles = ["hvsync_generator.v", "sprite_bitmap.v", "sprite_renderer.v", "cpu8.v", "femto8.json"];
var depends = [];
for (var dfile of dependfiles) {
var code = ab2str(fs.readFileSync('presets/verilog/' + dfile));
@ -201,7 +201,7 @@ describe('Worker', function() {
});
it('should compile verilog assembler file (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm'));
var dependfiles = ["hvsync_generator.v", "font_cp437_8x8.v", "ram.v", "tile_renderer.v", "sprite_scanline_renderer.v", "lfsr.v", "sound_generator.v", "cpu16.v", "cpu_platform.v"];
var dependfiles = ["hvsync_generator.v", "font_cp437_8x8.v", "ram.v", "tile_renderer.v", "sprite_scanline_renderer.v", "lfsr.v", "sound_generator.v", "cpu16.v", "cpu_platform.v", "femto16.json"];
var depends = [];
for (var dfile of dependfiles) {
var code = ab2str(fs.readFileSync('presets/verilog/' + dfile));