6502/8bitworkshop
1
0
Fork 0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-06-12 03:29:31 +00:00
Code Issues Projects Releases Wiki Activity

only use audio when spkr output present

Browse Source
This commit is contained in:
Steven Hugg 2018-02-21 12:54:53 -06:00
parent 20ddb8a11f
commit 7e04a15670
2 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/platform/verilog.js
View File

@ -268,7 +268,7 @@ var VerilogPlatform = function(mainElement, options) {
} }
function updateVideoFrame() { function updateVideoFrame() {
useAudio = gen.spkr !== 'undefined'; useAudio = (audio != null);
debugCond = self.getDebugCallback(); debugCond = self.getDebugCallback();
var i=videoWidth-10; var i=videoWidth-10;
var trace=inspect_obj && inspect_sym; var trace=inspect_obj && inspect_sym;
@ -448,7 +448,6 @@ var VerilogPlatform = function(mainElement, options) {
case 39: scope_time_x++; dirty=true; break; case 39: scope_time_x++; dirty=true; break;
} }
}); });
audio = new SampleAudio(AUDIO_FREQ);
idata = video.getFrameData(); idata = video.getFrameData();
timer = new AnimationTimer(frameRate, function() { timer = new AnimationTimer(frameRate, function() {
if (!self.isRunning()) if (!self.isRunning())
@ -459,6 +458,7 @@ var VerilogPlatform = function(mainElement, options) {
else else
updateScopeFrame(); updateScopeFrame();
}); });
trace_buffer = new Uint32Array(0x10000);
} }
this.printErrorCodeContext = function(e, code) { this.printErrorCodeContext = function(e, code) {
@ -482,14 +482,24 @@ var VerilogPlatform = function(mainElement, options) {
this.printErrorCodeContext(e, output.code); this.printErrorCodeContext(e, output.code);
throw e; throw e;
} }
// compile Verilog code
var base = new VerilatorBase(); var base = new VerilatorBase();
gen = new mod(base); gen = new mod(base);
gen.__proto__ = base; gen.__proto__ = base;
current_output = output; current_output = output;
ports_and_signals = current_output.ports; // TODO: current_output.ports.concat(current_output.signals); ports_and_signals = current_output.ports;
trace_buffer = new Uint32Array(0x10000);
trace_index = 0; trace_index = 0;
// power on module
this.poweron(); this.poweron();
// stop/start audio
if (audio && gen.spkr === undefined) {
audio.stop();
audio = null;
} else if (!audio && gen.spkr !== undefined) {
audio = new SampleAudio(AUDIO_FREQ);
if (this.isRunning())
audio.start();
}
} }
this.isRunning = function() { this.isRunning = function() {
@ -497,11 +507,11 @@ var VerilogPlatform = function(mainElement, options) {
} }
this.pause = function() { this.pause = function() {
timer.stop(); timer.stop();
if (gen.spkr !== undefined) audio.stop(); if (audio) audio.stop();
} }
this.resume = function() { this.resume = function() {
timer.start(); timer.start();
if (gen.spkr !== undefined) audio.start(); if (audio) audio.start();
} }
this.poweron = function() { this.poweron = function() {

2
src/ui.js
View File

@ -619,6 +619,7 @@ function setupBreakpoint() {
function _pause() { function _pause() {
if (platform.isRunning()) { if (platform.isRunning()) {
platform.pause(); platform.pause();
console.log("Paused");
} }
$("#dbg_pause").addClass("btn_stopped"); $("#dbg_pause").addClass("btn_stopped");
$("#dbg_go").removeClass("btn_active"); $("#dbg_go").removeClass("btn_active");
@ -633,6 +634,7 @@ function pause() {
function _resume() { function _resume() {
if (! platform.isRunning()) { if (! platform.isRunning()) {
platform.resume(); platform.resume();
console.log("Resumed");
} }
$("#dbg_pause").removeClass("btn_stopped"); $("#dbg_pause").removeClass("btn_stopped");
$("#dbg_go").addClass("btn_active"); $("#dbg_go").addClass("btn_active");