mirror of
https://github.com/sehugg/8bitworkshop.git
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verilog: scope updates, show js code, simple cpu
This commit is contained in:
Steven Hugg
parent
a541b3c4e6
commit
80588fcb31
196
presets/verilog/simple_cpu.v
Normal file
196
presets/verilog/simple_cpu.v
Normal file
@ -0,0 +1,196 @@
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`define OP_LOAD_A 4'h0
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`define OP_LOAD_B 4'h1
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`define OP_ADD 4'h2
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`define OP_SUB 4'h3
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`define OP_INC 4'h4
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`define OP_DEC 4'h5
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`define OP_ASL 4'h6
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`define OP_LSR 4'h7
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`define OP_OR 4'h8
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`define OP_AND 4'h9
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`define OP_XOR 4'ha
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module ALU(A, B, Y, aluop);
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input [7:0] A;
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input [7:0] B;
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output [8:0] Y;
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input [3:0] aluop;
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always @(*)
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case (aluop)
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`OP_LOAD_A: Y = {1'b0, A};
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`OP_LOAD_B: Y = {1'b0, B};
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`OP_ADD: Y = A + B;
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`OP_SUB: Y = A - B;
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`OP_INC: Y = A + 1;
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`OP_DEC: Y = A - 1;
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`OP_ASL: Y = {A[7], A + A};
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`OP_LSR: Y = {A[0], A >> 1};
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`OP_OR: Y = {1'b0, A | B};
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`OP_AND: Y = {1'b0, A & B};
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`OP_XOR: Y = {1'b0, A ^ B};
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default: Y = 9'bx;
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endcase
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endmodule
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`define REG_A 1'b0
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`define REG_B 1'b1
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`define I_CONST(r,x) { 2'b00, r, x }
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`define I_LOAD_ADDR(r,addr) { 3'b010, r, addr }
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`define I_STORE_ADDR(r,addr) { 3'b011, r, addr }
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`define I_COMPUTE(r,op) { 3'b100, r, op }
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`define I_RESET 8'hff
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module CPU(clk, reset, address, data_in, data_out, write);
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input clk, reset;
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output [7:0] address;
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input [7:0] data_in;
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output [7:0] data_out;
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output write;
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reg [7:0] ip;
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reg [7:0] opcode;
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reg [3:0] aluop;
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reg [7:0] A, B;
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reg [8:0] Y;
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reg [1:0] state;
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reg [2:0] action;
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reg carry;
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reg zero;
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localparam NOOP = 0;
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localparam MAKE_CONST = 1;
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localparam LOAD_ADDR = 2;
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localparam STORE_ADDR = 3;
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localparam COMPUTE = 4;
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wire load_const = opcode[3:1] == 3'b111;
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ALU alu(.A(A), .B(B), .Y(Y), .aluop(aluop));
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always @(posedge clk)
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if (reset) begin
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state <= 0;
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write <= 0;
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end else begin
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case (state)
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// state 0: reset
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0: begin
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ip <= 8'h80;
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write <= 0;
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state <= 1;
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end
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// state 1: select opcode address
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1: begin
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address <= ip;
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ip <= ip + 1;
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write <= 0;
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state <= 2;
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end
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// state 2: read/decode opcode
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2: begin
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casez (data_in)
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8'b00??????: begin
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action <= MAKE_CONST;
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if (data_in[5])
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B <= {3'b0, data_in[4:0]};
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else
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A <= {3'b0, data_in[4:0]};
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state <= 1;
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end
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8'b010?????: begin
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action <= LOAD_ADDR;
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address <= {4'b0, data_in[3:0]};
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state <= 3;
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end
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8'b011?????: begin
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action <= STORE_ADDR;
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address <= {4'b0, data_in[3:0]};
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state <= 3;
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end
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8'b100?????: begin
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action <= COMPUTE;
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aluop <= data_in[3:0];
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state <= 3;
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end
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default: begin
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action <= NOOP;
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state <= 0; // reset
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end
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endcase
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opcode <= data_in;
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end
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// state 3: perform action
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3: begin
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if (action == LOAD_ADDR) begin
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if (opcode[4])
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B <= data_in;
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else
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A <= data_in;
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end else if (action == STORE_ADDR) begin
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if (opcode[4])
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data_out <= B;
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else
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data_out <= A;
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write <= 1;
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end else if (action == COMPUTE) begin
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if (opcode[4])
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B <= Y[7:0];
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else
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A <= Y[7:0];
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carry <= Y[8];
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zero <= ~|Y;
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end
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state <= 1; // repeat loop at state 1
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end
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endcase
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end
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endmodule
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module test_CPU_top(clk, reset, address_bus, to_cpu, from_cpu, write_enable);
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input clk, reset;
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output [7:0] address_bus;
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output reg [7:0] to_cpu;
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output [7:0] from_cpu;
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output write_enable;
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reg [7:0] ram[128];
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reg [7:0] rom[128];
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CPU cpu(.clk(clk),
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.reset(reset),
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.address(address_bus),
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.data_in(to_cpu),
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.data_out(from_cpu),
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.write(write_enable));
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// does not work as (posedge clk)
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always @(*)
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if (write_enable)
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ram[address_bus[6:0]] = from_cpu;
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else if (address_bus[7] == 0)
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to_cpu = ram[address_bus[6:0]];
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else
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to_cpu = rom[address_bus[6:0]];
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initial begin
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// address 0x80
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rom['h00] = `I_CONST(`REG_A, 5'h1f);
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rom['h01] = `I_COMPUTE(`REG_A, `OP_ASL);
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rom['h02] = `I_COMPUTE(`REG_A, `OP_ASL);
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rom['h03] = `I_COMPUTE(`REG_A, `OP_ASL);
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rom['h04] = `I_COMPUTE(`REG_A, `OP_ASL);
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rom['h05] = `I_COMPUTE(`REG_B, `OP_LOAD_A);
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rom['h06] = `I_STORE_ADDR(`REG_B, 4'd1);
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rom['h07] = `I_LOAD_ADDR(`REG_B, 4'd1);
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rom['h08] = `I_RESET;
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end
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endmodule
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@ -17,6 +17,7 @@ module sprite_multiple_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
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reg [7:0] paddle_y;
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reg [7:0] enemy_x = 128;
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reg [7:0] enemy_y = 128;
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reg enemy_dir = 0;
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reg [15:0] track_pos = 0;
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reg [7:0] speed = 31;
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@ -73,17 +74,29 @@ module sprite_multiple_top(clk, hsync, vsync, rgb, hpaddle, vpaddle);
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if (!vpaddle) paddle_y <= vpos[7:0];
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end
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wire enemy_hit_left = (enemy_x == 64);
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wire enemy_hit_right = (enemy_x == 192);
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wire enemy_hit_edge = enemy_hit_left || enemy_hit_right;
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always @(posedge vsync)
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begin
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player_x <= paddle_x;
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player_y <= 180;
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track_pos <= track_pos + {11'b0,speed[7:4]};
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enemy_y <= enemy_y + {3'b0, speed[7:4]};
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if (enemy_hit_edge)
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enemy_dir <= !enemy_dir;
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if (enemy_dir ^ enemy_hit_edge)
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enemy_x <= enemy_x + 1;
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else
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enemy_x <= enemy_x - 1;
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// collision check?
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if (frame_collision)
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speed <= 16;
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else if (speed < 255)
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else if (speed < ~paddle_y)
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speed <= speed + 1;
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else
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speed <= speed - 1;
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end
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reg frame_collision;
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@ -92,16 +92,17 @@ function VerilatorBase() {
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this.ticks = function() { return totalTicks; }
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this.setTicks = function(T) { totalTicks = T|0; }
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var RESET_TICKS = 1000;
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this.reset2 = function() {
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this.__reset = function() {
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if (this.reset !== undefined) {
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totalTicks = 0;
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this.reset = 0;
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this.tick2();
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this.reset = 1;
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for (var i=0; i<RESET_TICKS; i++)
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this.tick2();
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}
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}
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this.__unreset = function() {
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if (this.reset !== undefined) {
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this.reset = 0;
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}
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}
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@ -169,6 +170,18 @@ var VerilogPlatform = function(mainElement, options) {
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var switches = [0];
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var inspect_obj, inspect_sym;
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var inspect_data = new Uint32Array(videoWidth * videoHeight);
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var scope_time_x = 0;
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var scope_y_offset = 0;
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var scope_max_y = 0;
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var yposlist = [];
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var lasty = [];
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var lastval = [];
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var ports_and_signals;
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var trace_buffer;
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var trace_index;
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var mouse_pressed;
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var dirty = false;
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this.getPresets = function() { return VERILOG_PRESETS; }
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@ -243,14 +256,31 @@ var VerilogPlatform = function(mainElement, options) {
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video.updateFrame();
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updateInspectionPostFrame();
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self.restartDebugState();
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gen.__unreset();
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}
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var yposlist = [];
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var lasty = [];
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function fillTraceBuffer(count) {
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var arr = ports_and_signals;
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var max_index = Math.min(trace_buffer.length, trace_index + count);
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while (trace_index < max_index) {
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gen.clk ^= 1;
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gen.eval();
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for (var i=0; i<arr.length; i++) {
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var v = arr[i];
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var z = gen[v.name];
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trace_buffer[trace_index++] = z;
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}
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dirty = true;
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}
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gen.__unreset();
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}
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function updateScopeFrame() {
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var arr = current_output.ports;
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var arr = ports_and_signals;
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if (!arr) return;
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fillTraceBuffer(Math.floor(videoWidth/4) * arr.length);
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if (!dirty) return;
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dirty = false;
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for (var i=0; i<idata.length; i++) {
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if (idata[i])
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idata[i] = 0; //<<= 1;
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@ -258,18 +288,18 @@ var VerilogPlatform = function(mainElement, options) {
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var COLOR_SIGNAL = 0xff22ff22;
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var COLOR_BORDER = 0xff662222;
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var COLOR_TRANS_SIGNAL = 0xff226622;
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var COLOR_BLIP_SIGNAL = 0xff226622;
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var j = 0;
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for (var x=0; x<videoWidth; x++) {
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gen.clk ^= 1;
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gen.eval();
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var yb = 8;
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var y1 = 0;
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var y1 = scope_y_offset;
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for (var i=0; i<arr.length; i++) {
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var v = arr[i];
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var lo = 0; // TODO? v.ofs?
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var hi = v.len ? ((2 << v.len)-1) : 1;
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var ys = hi>1 ? v.len*2+8 : 8;
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var y2 = y1+ys;
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var z = gen[v.name];
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var z = trace_buffer[j++];
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var y = Math.round(y2 - ys*((z-lo)/hi));
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yposlist[i] = y2;
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var ly = lasty[i];
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@ -279,22 +309,29 @@ var VerilogPlatform = function(mainElement, options) {
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idata[x + ly*videoWidth] = COLOR_TRANS_SIGNAL;
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}
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}
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idata[x + y*videoWidth] = lastval[i]==z ? COLOR_SIGNAL : COLOR_BLIP_SIGNAL;
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lasty[i] = y;
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//idata[x + y1*videoWidth] = COLOR_BORDER;
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//idata[x + y2*videoWidth] = COLOR_BORDER;
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idata[x + y*videoWidth] = COLOR_SIGNAL;
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lastval[i] = z;
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y1 += ys+yb;
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}
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}
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scope_max_y = y1;
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video.updateFrame();
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// draw labels
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var ctx = video.getContext();
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for (var i=0; i<arr.length; i++) {
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var v = arr[i];
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ctx.fillStyle = v.name == inspect_sym ? "yellow" : "white";
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ctx.fillText(v.name, 1, yposlist[i]);
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//ctx.textAlign = 'right';
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//ctx.fillText(""+gen[v.name], videoWidth-1, yposlist[i]);
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var name = v.name;
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ctx.fillStyle = name == inspect_sym ? "yellow" : "white";
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name = name.replace(/__DOT__/g,'.');
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ctx.textAlign = 'left';
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ctx.fillText(name, 1, yposlist[i]);
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if (scope_time_x > 0) {
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ctx.fillRect(scope_time_x, 0, 1, 4000);
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ctx.textAlign = 'right';
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var value = arr.length * scope_time_x + i;
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ctx.fillText(""+trace_buffer[value], videoWidth-1, yposlist[i]);
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}
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}
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}
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@ -312,8 +349,25 @@ var VerilogPlatform = function(mainElement, options) {
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ctx.textAlign = "left";
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setKeyboardFromMap(video, switches, VERILOG_KEYCODE_MAP);
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$(video.canvas).mousemove(function(e) {
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paddle_x = clamp(8,240,Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width() - 20));
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paddle_y = clamp(8,240,Math.floor(e.offsetY * video.canvas.height / $(video.canvas).height() - 20));
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var new_x = Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width() - 20);
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var new_y = Math.floor(e.offsetY * video.canvas.height / $(video.canvas).height() - 20);
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if (mouse_pressed) {
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scope_y_offset = clamp(-scope_max_y, 0, scope_y_offset + new_y - paddle_y);
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scope_time_x = Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width() - 16);
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dirty = true;
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}
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paddle_x = clamp(8, 240, new_x);
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paddle_y = clamp(8, 240, new_y);
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});
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$(video.canvas).mousedown(function(e) {
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scope_time_x = Math.floor(e.offsetX * video.canvas.width / $(video.canvas).width() - 16);
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mouse_pressed = true;
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e.target.setCapture();
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dirty = true;
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});
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$(video.canvas).mouseup(function(e) {
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mouse_pressed = false;
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e.target.releaseCapture();
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});
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audio = new SampleAudio(AUDIO_FREQ);
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idata = video.getFrameData();
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@ -354,6 +408,9 @@ var VerilogPlatform = function(mainElement, options) {
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gen = new mod(base);
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gen.__proto__ = base;
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current_output = output;
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ports_and_signals = current_output.ports.concat(current_output.signals);
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trace_buffer = new Uint32Array(0x10000);
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trace_index = 0;
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this.poweron();
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}
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@ -374,7 +431,10 @@ var VerilogPlatform = function(mainElement, options) {
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this.reset();
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}
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this.reset = function() {
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gen.reset2();
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gen.__reset();
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trace_index = 0;
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trace_buffer.fill(0);
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dirty = true;
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}
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this.tick = function() {
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gen.tick2();
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12
src/ui.js
12
src/ui.js
@ -37,6 +37,7 @@ var platform_id;
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var platform; // platform object
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var originalFileID;
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var originalText;
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var userPaused;
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var toolbar = $("#controls_top");
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@ -508,7 +509,7 @@ function setCompileOutput(data) {
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try {
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//console.log("Loading ROM length", rom.length);
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platform.loadROM(getCurrentPresetTitle(), rom);
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resume();
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if (!userPaused) resume();
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current_output = rom;
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resetProfiler();
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toolbar.removeClass("has-errors");
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@ -625,6 +626,7 @@ function _pause() {
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function pause() {
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clearBreakpoint();
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_pause();
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userPaused = true;
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}
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function _resume() {
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@ -640,6 +642,7 @@ function resume() {
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if (! platform.isRunning() )
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editor.setSelection(editor.getCursor()); // TODO??
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_resume();
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userPaused = false;
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}
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function singleStep() {
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@ -765,7 +768,7 @@ function updateDisassembly() {
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var div = $("#disassembly");
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if (div.is(':visible')) {
|
||||
var state = lastDebugState || platform.saveState();
|
||||
var pc = state.c.PC;
|
||||
var pc = state.c ? state.c.PC : 0;
|
||||
if (assemblyfile && assemblyfile.text) {
|
||||
var asmtext = assemblyfile.text;
|
||||
if (platform_id == 'base_z80') { // TODO
|
||||
@ -818,6 +821,9 @@ function updateDisassembly() {
|
||||
disasmview.setValue(text);
|
||||
disasmview.setCursor(selline, 0);
|
||||
jumpToLine(disasmview, selline);
|
||||
} else if (current_output.code) {
|
||||
// show verilog javascript
|
||||
disasmview.setValue(current_output.code);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1253,7 +1259,7 @@ function setupDebugControls(){
|
||||
if (platform.getProbe) {
|
||||
$("#dbg_profile").click(toggleProfileWindow).show();
|
||||
}
|
||||
if (platform.saveState && platform_id != 'verilog') { // TODO: only show if listing or disasm available
|
||||
if (platform.saveState) { // TODO: only show if listing or disasm available
|
||||
$("#dbg_disasm").click(toggleDisassembly).show();
|
||||
}
|
||||
$("#disassembly").hide();
|
||||
|
||||
@ -1023,7 +1023,9 @@ function assembleNAKEN(code, platform) {
|
||||
}
|
||||
|
||||
function detectModuleName(code) {
|
||||
var m = /\bmodule\s+(\w+_top)/.exec(code) || /\bmodule\s+(\w+)/.exec(code);
|
||||
var m = /\bmodule\s+(\w+_top)\b/.exec(code)
|
||||
|| /\bmodule\s+(top)\b/.exec(code)
|
||||
|| /\bmodule\s+(\w+)\b/.exec(code);
|
||||
return m ? m[1] : null;
|
||||
}
|
||||
|
||||
|
||||
@ -55,6 +55,17 @@ describe('Verilog Worker', function() {
|
||||
testVerilator('presets/verilog/lfsr.v');
|
||||
// TODO: how to include files?
|
||||
|
||||
//testVerilator('test/cli/verilog/t_tri_gate.v');
|
||||
testVerilator('test/cli/verilog/t_tri_gen.v', ['UNDRIVEN']);
|
||||
testVerilator('test/cli/verilog/t_tri_graph.v', ['UNDRIVEN']);
|
||||
testVerilator('test/cli/verilog/t_tri_ifbegin.v', ['UNDRIVEN']);
|
||||
testVerilator('test/cli/verilog/t_tri_inout.v');
|
||||
testVerilator('test/cli/verilog/t_tri_inout2.v');
|
||||
testVerilator('test/cli/verilog/t_tri_pullup.v', ['UNDRIVEN']);
|
||||
testVerilator('test/cli/verilog/t_tri_select_unsized.v', ['WIDTH']);
|
||||
testVerilator('test/cli/verilog/t_tri_unconn.v', ['PINCONNECTEMPTY']);
|
||||
testVerilator('test/cli/verilog/t_tri_various.v', ['UNDRIVEN']);
|
||||
|
||||
/* TODO: fix tests
|
||||
testVerilator('test/cli/verilog/t_order_doubleloop.v', ['BLKSEQ']);
|
||||
testVerilator('test/cli/verilog/t_alw_combdly.v');
|
||||
|
||||
43
test/cli/verilog/t_tri_gen.v
Normal file
43
test/cli/verilog/t_tri_gen.v
Normal file
@ -0,0 +1,43 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
tri z0;
|
||||
tri z1;
|
||||
|
||||
updown #(0) updown0 (.z(z0));
|
||||
updown #(1) updown1 (.z(z1));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (z0 !== 0) $stop;
|
||||
if (z1 !== 1) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module updown #(parameter UP=0)
|
||||
(inout z);
|
||||
generate
|
||||
if (UP) begin
|
||||
t_up sub (.z);
|
||||
end
|
||||
else begin
|
||||
t_down sub (.z);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module t_up (inout tri1 z);
|
||||
endmodule
|
||||
|
||||
module t_down (inout tri0 z);
|
||||
endmodule
|
||||
27
test/cli/verilog/t_tri_graph.v
Normal file
27
test/cli/verilog/t_tri_graph.v
Normal file
@ -0,0 +1,27 @@
|
||||
// DESCRIPTION: Verilator: Unsupported tristate constructur error
|
||||
//
|
||||
// This is a compile only regression test of tristate handling for bug514
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [11:0] ck;
|
||||
|
||||
assign ck[1:0] = {1'bz,{1{1'b0}}};
|
||||
|
||||
test i_test (.clk (ck[1:0]));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module test (clk);
|
||||
|
||||
output wire [1:0] clk;
|
||||
|
||||
endmodule // test
|
||||
52
test/cli/verilog/t_tri_ifbegin.v
Normal file
52
test/cli/verilog/t_tri_ifbegin.v
Normal file
@ -0,0 +1,52 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
|
||||
module top (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
tri pad_io_h;
|
||||
tri pad_io_l;
|
||||
|
||||
sub sub (.*);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module sub (/*AUTOARG*/
|
||||
// Inouts
|
||||
pad_io_h, pad_io_l
|
||||
);
|
||||
|
||||
parameter USE = 1'b1;
|
||||
parameter DIFFERENTIAL = 1'b1;
|
||||
parameter BIDIR = 1'b1;
|
||||
|
||||
inout pad_io_h;
|
||||
inout pad_io_l;
|
||||
|
||||
wire [31:0] dqs_out_dtap_delay;
|
||||
|
||||
generate
|
||||
if (USE) begin: output_strobe
|
||||
wire aligned_os_oe;
|
||||
wire aligned_strobe;
|
||||
|
||||
if (BIDIR) begin
|
||||
reg sig_h_r = 1'b0;
|
||||
reg sig_l_r = 1'b0;
|
||||
always @* begin
|
||||
sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz;
|
||||
if (DIFFERENTIAL)
|
||||
sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz;
|
||||
end
|
||||
assign pad_io_h = sig_h_r;
|
||||
if (DIFFERENTIAL)
|
||||
assign pad_io_l = sig_l_r;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
19
test/cli/verilog/t_tri_inout.v
Normal file
19
test/cli/verilog/t_tri_inout.v
Normal file
@ -0,0 +1,19 @@
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2008 by Lane Brooks
|
||||
|
||||
module top (input A, input B, input SEL, output Y1, output Y2, output Z);
|
||||
io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1));
|
||||
pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2));
|
||||
assign Z = 1'bz;
|
||||
endmodule
|
||||
|
||||
module pass (input A, input OE, inout Z, output Y);
|
||||
io io(.A(A), .OE(OE), .Z(Z), .Y(Y));
|
||||
assign Z = 1'bz;
|
||||
endmodule
|
||||
|
||||
module io (input A, input OE, inout Z, output Y);
|
||||
assign Z = (OE) ? A : 1'bz;
|
||||
assign Y = Z;
|
||||
assign Z = 1'bz;
|
||||
endmodule
|
||||
77
test/cli/verilog/t_tri_inout2.v
Normal file
77
test/cli/verilog/t_tri_inout2.v
Normal file
@ -0,0 +1,77 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2008 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [2:0] in;
|
||||
|
||||
|
||||
wire a,y,y_fixed;
|
||||
wire b = in[0];
|
||||
wire en = in[1];
|
||||
|
||||
|
||||
pullup(a);
|
||||
|
||||
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
|
||||
|
||||
initial in=0;
|
||||
initial en=0;
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
|
||||
|
||||
in <= in + 1;
|
||||
|
||||
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
|
||||
if (en) begin
|
||||
// driving b
|
||||
// a should be b
|
||||
// y and yfix should also be b
|
||||
if (a!=b || y != b || y_fixed != b) begin
|
||||
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
|
||||
$stop;
|
||||
end
|
||||
|
||||
end else begin
|
||||
// not driving b
|
||||
// a should be 1 (pullup)
|
||||
// y and yfix shold be 1
|
||||
if (a!=1 || y != 1 || y_fixed != 1) begin
|
||||
$display( "Expected a,y,yfix == 1");
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
if (in==3) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ChildA(inout A, input B, input en, output Y, output Yfix);
|
||||
|
||||
// workaround
|
||||
wire a_in = A;
|
||||
|
||||
ChildB childB(.A(A), .Y(Y));
|
||||
assign A = en ? B : 1'bz;
|
||||
|
||||
|
||||
ChildB childBfix(.A(a_in),.Y(Yfix));
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
module ChildB(input A, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
26
test/cli/verilog/t_tri_pullup.v
Normal file
26
test/cli/verilog/t_tri_pullup.v
Normal file
@ -0,0 +1,26 @@
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2008 by Lane Brooks
|
||||
|
||||
module top (input A, input OE, output X, output Y, output Z);
|
||||
|
||||
pullup p1(Z);
|
||||
assign Z = OE ? A : 1'bz;
|
||||
|
||||
pulldown p2(Y);
|
||||
assign Y = OE ? A : 1'bz;
|
||||
|
||||
pass pass(.A(A), .OE(OE), .X(X));
|
||||
pullup_module p(X);
|
||||
endmodule
|
||||
|
||||
module pass (input A, input OE, inout X);
|
||||
io io(.A(A), .OE(OE), .X(X));
|
||||
endmodule
|
||||
|
||||
module io (input A, input OE, inout X);
|
||||
assign X = (OE) ? A : 1'bz;
|
||||
endmodule
|
||||
|
||||
module pullup_module (output X);
|
||||
pullup p1(X);
|
||||
endmodule
|
||||
27
test/cli/verilog/t_tri_select_unsized.v
Normal file
27
test/cli/verilog/t_tri_select_unsized.v
Normal file
@ -0,0 +1,27 @@
|
||||
// DESCRIPTION: Verilator: Test of selection with unsized Z.
|
||||
//
|
||||
// Test selecting Z when size is not explicit. Issue 510.
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Jeremy Bennett.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [1:0] b;
|
||||
wire [1:0] c;
|
||||
wire [0:0] d; // Explicit width due to issue 508
|
||||
wire [0:0] e;
|
||||
|
||||
// This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It
|
||||
// does require the tri-state Z. Since we get the same effect if b is
|
||||
// dimensioned [0:0], this may be connected to issue 508.
|
||||
assign b[1:0] = clk ? 2'bx : 'bz;
|
||||
assign c[1:0] = clk ? 2'bz : 'bx;
|
||||
assign d = clk ? 1'bx : 'bz;
|
||||
assign e = clk ? 1'bz : 'bx;
|
||||
|
||||
endmodule // t
|
||||
124
test/cli/verilog/t_tri_unconn.v
Normal file
124
test/cli/verilog/t_tri_unconn.v
Normal file
@ -0,0 +1,124 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2012 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
|
||||
wire one = '1;
|
||||
wire z0 = 'z;
|
||||
wire z1 = 'z;
|
||||
wire z2 = 'z;
|
||||
wire z3 = 'z;
|
||||
wire tog = cyc[0];
|
||||
|
||||
// verilator lint_off PINMISSING
|
||||
t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing
|
||||
t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn());
|
||||
t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0));
|
||||
t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
|
||||
t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
|
||||
t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect
|
||||
t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one));
|
||||
t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one));
|
||||
t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
|
||||
t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
|
||||
|
||||
t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing
|
||||
t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn());
|
||||
t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1));
|
||||
t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
|
||||
t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect
|
||||
t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
|
||||
t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one));
|
||||
t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one));
|
||||
t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
|
||||
t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
|
||||
|
||||
t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing
|
||||
t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn());
|
||||
t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2));
|
||||
t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
|
||||
t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
|
||||
t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
|
||||
t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one));
|
||||
t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one));
|
||||
t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
|
||||
t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
|
||||
|
||||
t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing
|
||||
t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn());
|
||||
t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3));
|
||||
t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
|
||||
t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
|
||||
t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
|
||||
t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one));
|
||||
t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one));
|
||||
t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
|
||||
t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
|
||||
// verilator lint_on PINMISSING
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module t_tri0
|
||||
(line, expval, tn);
|
||||
input integer line;
|
||||
input expval;
|
||||
input tn; // Illegal to be inout; spec requires net connection to any inout
|
||||
tri0 tn;
|
||||
wire clk = t.clk;
|
||||
always @(posedge clk) if (tn !== expval) begin
|
||||
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module t_tri1
|
||||
(line, expval, tn);
|
||||
input integer line;
|
||||
input expval;
|
||||
input tn;
|
||||
tri1 tn;
|
||||
wire clk = t.clk;
|
||||
always @(posedge clk) if (tn !== expval) begin
|
||||
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module t_tri2
|
||||
(line, expval, tn);
|
||||
input integer line;
|
||||
input expval;
|
||||
input tn;
|
||||
pulldown(tn);
|
||||
wire clk = t.clk;
|
||||
always @(posedge clk) if (tn !== expval) begin
|
||||
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module t_tri3
|
||||
(line, expval, tn);
|
||||
input integer line;
|
||||
input expval;
|
||||
input tn;
|
||||
pullup(tn);
|
||||
wire clk = t.clk;
|
||||
always @(negedge clk) if (tn !== expval) begin
|
||||
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
|
||||
end
|
||||
endmodule
|
||||
211
test/cli/verilog/t_tri_various.v
Normal file
211
test/cli/verilog/t_tri_various.v
Normal file
@ -0,0 +1,211 @@
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2008 by Lane Brooks
|
||||
|
||||
module t (clk);
|
||||
input clk;
|
||||
|
||||
reg [31:0] state; initial state=0;
|
||||
|
||||
wire A = state[0];
|
||||
wire OE = state[1];
|
||||
wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
|
||||
wire [3:0] Z10;
|
||||
wire Z11;
|
||||
|
||||
Test1 test1(/*AUTOINST*/
|
||||
// Inouts
|
||||
.Z1 (Z1),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test2 test2(/*AUTOINST*/
|
||||
// Inouts
|
||||
.Z2 (Z2),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test3 test3(/*AUTOINST*/
|
||||
// Inouts
|
||||
.Z3 (Z3),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test4 test4(/*AUTOINST*/
|
||||
// Outputs
|
||||
.Z4 (Z4),
|
||||
// Inouts
|
||||
.Z5 (Z5));
|
||||
|
||||
Test5 test5(/*AUTOINST*/
|
||||
// Inouts
|
||||
.Z6 (Z6),
|
||||
.Z7 (Z7),
|
||||
.Z8 (Z8),
|
||||
.Z9 (Z9),
|
||||
// Inputs
|
||||
.OE (OE));
|
||||
|
||||
Test6 test6(/*AUTOINST*/
|
||||
// Inouts
|
||||
.Z10 (Z10[3:0]),
|
||||
// Inputs
|
||||
.OE (OE));
|
||||
|
||||
Test7 test7(/*AUTOINST*/
|
||||
// Outputs
|
||||
.Z11 (Z11),
|
||||
// Inputs
|
||||
.state (state[2:0]));
|
||||
|
||||
always @(posedge clk) begin
|
||||
state <= state + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n",
|
||||
$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11);
|
||||
`endif
|
||||
|
||||
if(state == 0) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests pullups
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b1) $stop;
|
||||
if(Z7 !== 1'b0) $stop;
|
||||
if(Z8 !== 1'b0) $stop;
|
||||
if(Z9 !== 1'b1) $stop;
|
||||
if(Z10 !== 4'b0001) $stop;
|
||||
if(Z11 !== 1'b0) $stop;
|
||||
end
|
||||
else if(state == 1) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests pullup
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b1) $stop;
|
||||
if(Z7 !== 1'b0) $stop;
|
||||
if(Z8 !== 1'b0) $stop;
|
||||
if(Z9 !== 1'b1) $stop;
|
||||
if(Z10 !== 4'b0001) $stop;
|
||||
if(Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if(state == 2) begin
|
||||
if(Z1 !== 1'b0) $stop; // tests output driver low
|
||||
if(Z2 !== 1'b0) $stop;
|
||||
if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b0) $stop;
|
||||
if(Z7 !== 1'b1) $stop;
|
||||
if(Z8 !== 1'b1) $stop;
|
||||
if(Z9 !== 1'b0) $stop;
|
||||
if(Z10 !== 4'b0010) $stop;
|
||||
//if(Z11 !== 1'bx) $stop; // Doesn't matter
|
||||
end
|
||||
else if(state == 3) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests output driver high
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b0) $stop;
|
||||
if(Z7 !== 1'b1) $stop;
|
||||
if(Z8 !== 1'b1) $stop;
|
||||
if(Z9 !== 1'b0) $stop;
|
||||
if(Z10 !== 4'b0010) $stop;
|
||||
if(Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if(state == 4) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
pullup(Z1);
|
||||
pullup(Z2);
|
||||
pullup(Z3);
|
||||
pullup(Z4);
|
||||
pullup(Z5);
|
||||
pullup(Z6);
|
||||
pulldown(Z7);
|
||||
pullup(Z8);
|
||||
pulldown(Z9);
|
||||
pulldown pd10[3:0] (Z10);
|
||||
endmodule
|
||||
|
||||
|
||||
module Test1(input OE, input A, inout Z1);
|
||||
assign Z1 = (OE) ? A : 1'bz;
|
||||
endmodule
|
||||
|
||||
module Test2(input OE, input A, inout Z2);
|
||||
assign Z2 = (OE) ? A : 1'bz;
|
||||
endmodule
|
||||
|
||||
|
||||
// mixed low-Z and tristate
|
||||
module Test3(input OE, input A, inout Z3);
|
||||
assign Z3 = (OE) ? A : 1'bz;
|
||||
assign Z3 = 1'b1;
|
||||
endmodule
|
||||
|
||||
|
||||
// floating output and inout
|
||||
`ifndef VERILATOR
|
||||
// Note verilator doesn't know to make Z4 a tristate unless marked an inout
|
||||
`endif
|
||||
module Test4(output Z4, inout Z5);
|
||||
endmodule
|
||||
|
||||
|
||||
// AND gate tristates
|
||||
module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
|
||||
assign Z6 = (OE) ? 1'b0 : 1'bz;
|
||||
assign Z7 = (OE) ? 1'b1 : 1'bz;
|
||||
assign Z8 = (OE) ? 1'bz : 1'b0;
|
||||
assign Z9 = (OE) ? 1'bz : 1'b1;
|
||||
endmodule
|
||||
|
||||
// AND gate tristates
|
||||
module Test6(input OE, inout [3:0] Z10);
|
||||
wire [1:0] i;
|
||||
Test6a a (.OE(OE), .Z({Z10[0],Z10[1]}));
|
||||
Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]}));
|
||||
endmodule
|
||||
|
||||
module Test6a(input OE, inout [1:0] Z);
|
||||
assign Z = (OE) ? 2'b01 : 2'bzz;
|
||||
endmodule
|
||||
|
||||
module Test7(input [2:0] state, output reg Z11);
|
||||
always @(*) begin
|
||||
casez (state)
|
||||
3'b000: Z11 = 1'b0;
|
||||
3'b0?1: Z11 = 1'b1;
|
||||
default: Z11 = 1'bx;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This is not implemented yet
|
||||
//module Test3(input OE, input A, inout Z3);
|
||||
// always @(*) begin
|
||||
// if(OE) begin
|
||||
// Z3 = A;
|
||||
// end else begin
|
||||
// Z3 = 1'bz;
|
||||
// end
|
||||
// end
|
||||
//endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user