verilog: fixed $readmem bug

codemirror

@@ -1 +1 @@
-Subproject commit 4334727f0e07acd4541b0a7b8f81a5984cd4aafe
+Subproject commit 7ecf62faa30fb0de99b76609f16c58a7bf032820

doc/notes.txt

@@ -119,6 +119,9 @@ TODO:
   - CPU debugging
   - use $readmem for inline asm programs?
   - can't add control instructions b/c of split
+  - bad error msg if >2 moduels and top module doesn't match filename
+  - separate Scope View
+  - keyboard interface
 - single-stepping vector games makes screen fade
 - break on stack overflow, illegal op, bad access, BRK, etc
 - nes
@@ -164,6 +167,7 @@ TODO:
   - re-publish repo (bug: doesn't put all files in local repo after publishing)
   - allow text/binary change
   - importing from subtree commits to root anyway
+  - after publishing, only one file remaining
 - astrocade
 - keyboard shortcuts
   - ctrl+alt+l on ubuntu locks screen

src/worker/workermain.ts

@@ -1574,7 +1574,7 @@ function compileReadmemStmts(code, errors) {
       for (var i=0; i<lines.length; i++) {
         var line = lines[i].trim();
         if (line !== '') {
-          out += 'mem[' + i + ']=\'' + type + line + ';'
+          out += mem + '[' + i + ']=\'' + type + line + ';'
         }
       }
       return out;
@@ -1595,6 +1595,7 @@ function compileVerilator(step:BuildStep) {
   // compile verilog if files are stale
   var outjs = "main.js";
   if (staleFiles(step, [outjs])) {
+    // TODO: %Error: Specified --top-module 'ALU' isn't at the top level, it's under another cell 'cpu'
     var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?):(\d+)?[:]?\s*(.+)/i, 3, 4, step.path, 2);
     var verilator_mod = emglobal.verilator_bin({
       instantiateWasm: moduleInstFn('verilator_bin'),