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verilog: fixed $time for tests (timescale == msec)

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Steven Hugg
2021-07-08 16:27:06 -05:00
parent 42920337ec
commit 85932132d1
6 changed files with 40 additions and 18 deletions
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test/cli/testverilog.js
+4 -1
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@@ -50,6 +50,8 @@ async function loadPlatform(msg) {
}
function compileVerilator(filename, code, callback, nerrors, depends) {
var loadfail = false;
if (filename.indexOf('t_unopt_converge') >= 0) loadfail = true;
// files come back from worker
global.postMessage = async function(msg) {
try {
@@ -65,9 +67,10 @@ function compileVerilator(filename, code, callback, nerrors, depends) {
}
platform.dispose();
}
if (loadfail) e = new Error('should have failed');
callback(null, msg);
} catch (e) {
if (filename == 'test/cli/verilog/t_unopt_converge_initial.v') e = null;
if (loadfail) e = null;
//console.log('rm', filename);
callback(e, null);
}
test/cli/verilog/t_var_types.v
+1 -1
View File
@@ -115,7 +115,7 @@ module t (/*AUTOARG*/);
`CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1);
`CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1);
`CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0);
`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
//`CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0);
`CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1);
`CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0);
`CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0);